Process for forming barrier/seed structures for integrated circuits
First Claim
1. A method of processing a semiconductor wafer, comprising:
- providing a dielectric layer;
etching a feature within the dielectric layer, wherein the feature comprises a sidewall and a bottom surface;
depositing a non-conformal conductive layer over the dielectric layer and the bottom surface of the feature, wherein the conductive layer on the sidewall is less then 10% of the thickness of the conductive layer over the dielectric layer;
depositing a single conformal barrier and platability layer over the non-conformal conductive layer, and electroplating a conductive material to fill the feature.
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Abstract
A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
126 Citations
18 Claims
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1. A method of processing a semiconductor wafer, comprising:
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providing a dielectric layer;
etching a feature within the dielectric layer, wherein the feature comprises a sidewall and a bottom surface;
depositing a non-conformal conductive layer over the dielectric layer and the bottom surface of the feature, wherein the conductive layer on the sidewall is less then 10% of the thickness of the conductive layer over the dielectric layer;
depositing a single conformal barrier and platability layer over the non-conformal conductive layer, and electroplating a conductive material to fill the feature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification