Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure

• US 6,790,784 B2
• Filed: 04/24/2003
• Issued: 09/14/2004
• Est. Priority Date: 06/19/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Hsia, Wei-Jen, Catabay, Wilbur G.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US10/422,270
• Publication Number:
  US 20030207594A1
• Time in Patent Office: 509 Days
• Field of Search: 438/623, 438/634, 438/706, 438/723, 438/726, 438/725, 438/710, 438/714, 296/234, 298/25
• US Class Current: 438/726
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Claims

1. A process for forming an integrated circuit structure having at least one layer of low k material therein and a layer, formed from a low k dielectric layer, suitable for use as an etch stop and/or an etch mask which consists essentially of:

a) forming a first layer of low k dielectric material over previously formed portions of said integrated circuit structure; and

b) treating the upper surface of said first layer of low k dielectric material with a plasma formed from a reducing gas to form a first layer of densified dielectric material over the remainder of the underlying first layer of low k dielectric material whereby said first layer of densified dielectric material is capable of serving as an etch mask for etching of said underlying first layer of low k dielectric material;

c) forming a photoresist mask over said first layer of densified dielectric material;

d) patterning said first layer of densified dielectric material through said photoresist mask to form a first etch mask layer of densified dielectric material having a pattern of openings therein suitable for use in etching a corresponding pattern of openings in said underlying first layer of low k dielectric material;

e) then removing said photoresist mask before etching any openings in said underlying first layer of low k dielectric material through said pattern of openings in said first etch mask layer of densified dielectric material, whereby said first layer of densified dielectric material serves as an etch mask for subsequent etching of said underlying first layer of low k dielectric material;

f) then forming a second layer of low k dielectric material over said first etch mask of dielectric material; and

g) then treating the upper surface of said second layer of low k dielectric material with a plasma formed from a reducing gas to form a second layer of densified dielectric material over the remainder of said second layer of low k dielectric material.

2. The process of claim 1 including the further steps of:

a) forming a second photoresist mask over said second layer of densified dielectric material;

b) patterning said second layer of densified dielectric material through said second photoresist mask to form a second etch mask layer of densified dielectric material over said second layer of low k dielectric material, said second etch mask layer having a pattern of openings therein suitable for use in etching a corresponding pattern of openings in the underlying second layer of low k dielectric material;

c) then removing said second photoresist mask before etching any openings in said underlying second layer of low k dielectric material through said pattern of openings in said second etch mask layer of densified dielectric material;

d) etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer; and

e) etching a pattern of openings in said first low k dielectric layer through said first etch mask of dielectric material and said pattern of openings formed in said second layer of low k dielectric material.

3. The process of claim 2 wherein said step of etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer of dielectric material utilizes said first etch mask layer of dielectric material as an etch stop.

4. The process of claim 3 wherein:

a) said step of etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer further comprises forming trenches in said second layer of low k dielectric material; and

b) said step of etching a pattern of openings in said first low k dielectric layer through said first etch mask of dielectric material and said pattern of openings formed in said second layer of low k dielectric material further comprises forming vias in said first layer of low k dielectric material in communication with said trenches.

5. The process of claim 1 including the further steps of:

a) forming a second resist mask over said second layer of densified dielectric material;

b) patterning said second layer of densified dielectric material through said second photoresist mask to form a second etch mask layer of densified dielectric material over said second layer of low k dielectric material, said second etch mask layer having a pattern of openings therein suitable for use in etching a corresponding pattern of openings in the underlying second layer of low k dielectric material;

c) then removing said second photoresist mask before etching any openings in said underlying second layer of low k dielectric material through said pattern of openings in said second etch mask layer of densified dielectric material;

d) etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer of dielectric material;

e) forming a pattern of openings in said first etch mask layer through said pattern of openings formed in said second layer of low k dielectric material; and

f) etching a pattern of openings in said first layer of low k dielectric material through said pattern of openings in said first etch mask layer.

6. The process of claim 5 including the further steps of:

a) forming a third etch mask over said second etch mask layer, said third etch mask having openings larger than the openings in said pattern of openings in said second etch mask layer; and

b) etching said larger openings through;

i) said second etch mask layer; and

ii) said second layer of low k dielectric material;

down to said first etch mask layer, using said third etch mask;

whereby said structure will have a pattern of smaller openings formed in said first layer of low k dielectric material and a pattern of larger openings formed in said second layer of low k dielectric material and generally in registry with said pattern of smaller openings.

7. The process of claim 5 wherein said openings formed in said first and second layers of low k dielectric material and said first and second etch mask layers comprise vias, and said process includes the further steps of:

a) forming a trench mask over said second etch mask layer, said trench mask having openings larger than said vias in said second etch mask layer; and

b) etching said trenches through;

i) said second etch mask layer; and

ii) said second layer of low k dielectric material;

down to said first etch mask layer which then functions as an etch stop layer;

whereby said structure will have a pattern of vias formed in said first layer of low k dielectric material and a pattern of trenches formed in said second layer of low k dielectric material, with said trenches in registry with said vias.

8. The process of claim 1 including the further steps of:

a) forming a second photoresist mask over said second densified layer of dielectric material;

b) patterning said second layer of densified dielectric material through said second photoresist mask to form, over said second layer of low k dielectric material, a second etch mask layer of densified dielectric material;

c) then removing said second photoresist mask before etching any openings in said underlying second layer of low k dielectric material through said pattern of openings in said second etch mask layer of densified dielectric material; and

d) then etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer, with said first layer of densified dielectric material serving as an etch stop.

9. The process of claim 8, including the further step of etching a pattern of openings in said first layer of low k dielectric material through said openings in said second low k dielectric layer, and through said pattern of openings in said first etch mask layer thereunder.

10. The process of claim 8 including the further steps of:

a) forming a third etch mask over said second etch mask layer, said third mask having openings larger than the openings in said pattern of openings in said second etch mask layer; and

b) etching said larger openings through;

i) said third etch mask layer;

ii) said second etch mask layer of densified dielectric material;

ii) said second layer of low k dielectric material down to said first etch mask layer of densified dielectric material; and

c) then etching openings in said first layer of low k dielectric material through said first etch mask layer of dielectric material;

whereby said structure will have a pattern of smaller openings formed in said first layer of low k dielectric material and a pattern of larger openings formed in said second layer of low k dielectric material and generally in registry with said pattern of smaller openings.

11. The process of claim 1 including the further steps of:

a) forming over said second layer of densified dielectric material a second photoresist mask having openings therein larger than said openings in said first photoresist mask;

d) patterning said second layer of densified dielectric material through said second photoresist mask to form a second etch mask layer of densified dielectric material over said second layer of low k dielectric material;

said second etch mask layer of densified dielectric material having a pattern of openings therein comprising openings larger than said openings in said first etch mask layer of densified dielectric material, said openings in said second etch mask layer in registry with at least some of said openings in said first etch mask layer.

12. The process of claim 11 including the further steps of:

a) removing said second photoresist mask before etching any openings in said underlying second layer of low k dielectric material through said pattern of openings in said second etch mask layer of densified dielectric material;

b) etching a pattern of openings in said second layer of low k dielectric material through said pattern of openings in said second etch mask layer, thereby exposing said pattern of opening in said first etch mask layer; and

c) etching a pattern of openings in said first layer of low k dielectric material through said exposed pattern of openings in said first etch mask layer.

13. A process for forming a structure having a low k material therein which comprises:

a) forming a first layer of dielectric material over an integrated circuit structure;

b) forming a first layer of low k dielectric material over said first layer of dielectric material;

c) treating the upper surface of said first layer of low k dielectric material with a plasma formed from a non-oxidizing gas to form a first layer of densified dielectric material over the remainder of said first layer of low k dielectric material;

d) forming over said first layer of densified material a photoresist via mask having a pattern of via openings therein;

e) etching said first layer of densified material through said photoresist via mask to replicate in said first layer of densified material said pattern of via openings in said photoresist via mask;

f) removing said photoresist via mask before etching any openings in said underlying first layer of low k dielectric material through said pattern of via openings in said first etch mask layer of densified dielectric material, whereby said first layer of densified dielectric material serves as an etch mask for subsequent etching of said underlying first layer of low k dielectric material;

g) forming a second layer of low k dielectric material over said first layer of densified dielectric material;

h) treating the upper surface of said second layer of low k dielectric material with a plasma formed from a non-oxidizing gas to form a second layer of densified dielectric material over the remainder of said second layer of low k dielectric material;

i) forming over said second layer of densified dielectric material a photoresist trench mask having a pattern of trench openings therein in registry with said pattern of via openings in said first layer of densified material;

j) etching said pattern of trench openings in said second layer of densified dielectric material through said photoresist trench mask to replicate in said second layer of densified material said pattern of trenches in said photoresist trench mask;

k) then removing said photoresist trench mask before etching said second layer of low k dielectric material;

l) then etching said second layer of low k dielectric material through said trench openings formed in said second layer of densified dielectric material down to said first layer of densified dielectric material, thereby exposing, at the bottom of said trenches, said pattern of via openings formed in said first layer of densified material; and

m) then etching vias in said first layer of dielectric material and said first layer of low k dielectric material dielectric layers down to said integrated circuit structure through said exposed pattern of openings previously formed in said first layer of densified material at the bottom of said trenches.