Multiple chips bonded to packaging structure with low noise and multiple selectable functions

• US 6,791,192 B2
• Filed: 02/21/2003
• Issued: 09/14/2004
• Est. Priority Date: 05/19/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/371,506
• Publication Number:
  US 20030122240A1
• Time in Patent Office: 571 Days
• Field of Search: 257/778, 257/777, 257/775, 257/772, 257/786, 257/784, 257/734, 257/737, 257/738, 257/723, 257/616, 257/685, 257/686, 257/774, 257/431-433, 257/680
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Claims

1. A method of forming a chip package for semiconductor chips comprising:

forming a substrate with a top surface and a window therethrough, connecting at least two primary semiconductor chips each of which only partially overlies the window to the top surface of a printed circuit board by solder connections, and

connecting a secondary semiconductor chip located within the window to at least one of the two primary chips overlying the window in a chip-on-chip connection.

2. The method of claim 1 including connecting big solder balls to the top surface of the substrate aside from the primary semiconductor chips.

5. The method of claim 1 wherein the substrate comprises a printed circuit board.

6. The method of claim 2 wherein the substrate comprises a printed circuit board.

3. A chip package for semiconductor chips comprising:

a substrate with a top surface and a window therethrough,

at least two primary semiconductor chips each of which only partially overlies the window connected to the top surface of the substrate by solder connections,

a suspended secondary semiconductor chip located within the window, and

the suspended semiconductor chip being connected to at least one of the two primary chips overlying the window in a chip-on-chip connection.

4. The package of claim 3 including big solder balls connected to the top surface of the substrate aside from the primary semiconductor chips.

7. The method of claim 3 wherein the substrate comprises a printed circuit board.

8. The method of claim 7 wherein the substrate comprises a printed circuit board.