Chip mounting substrate, first level assembly, and second level assembly

• US 6,791,193 B2
• Filed: 03/05/2003
• Issued: 09/14/2004
• Est. Priority Date: 03/08/2002
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Watanabe, Shinya, Ozawa, Isao
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/382,020
• Publication Number:
  US 20040046262A1
• Time in Patent Office: 559 Days
• Field of Search: 257/731, 257/738, 257/777, 257/780, 257/781
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.

Claims

1. A chip mounting substrate comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands; and

a bent connection path embedded in the mounting base so as to connect the first lands with the second lands.

2. The chip mounting substrate of claim 1, wherein the mounting base is a BGA tape.

3. A chip mounting substrate comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands, wherein the first group of the first lands are connected to the first group of the second lands just above the first group of the first lands, and the second group of the first lands include a first intra substrate connection terminal insulated from the second land just above the first intra substrate connection terminal, and the second group of the second lands include a second inter level connection terminal insulated from the first land just below the second inter level connection terminal, and the first intra substrate connection terminal and the second inter level connection terminal are connected by the bent connection path having a stair-step shape.

4. A first level assembly comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands;

a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a bent connection path embedded in the mounting base so as to connect the first lands with the second lands; and

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.

5. The first level assembly of claim 4, wherein the mounting base is a BGA tape.

6. The first level assembly of claim 4, further comprising:

a heat sink contacted to the semiconductor chip.

7. The first level assembly of claim 4, wherein the sum of the thickness of the first and second lands is equal to or larger than the thickness of the semiconductor chip.

8. The first level assembly of claim 4, wherein the semiconductor chip is mounted in a facedown configuration on the chip mounting area.

9. A first level assembly comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands;

a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a plurality of joint balls disposed on the second lands, respectively;

an upper level mounting base defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed on the fourth surface so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a chip mounting area assigned adjacent to the upper level second lands on the fourth surface.

10. A first level assembly comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands;

a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a plurality of joint balls disposed on the second lands, respectively;

an upper level mounting base defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed on the fourth surface so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a chip mounting area assigned adjacent to the upper level second lands on the fourth surface, wherein the second group of the first lands include a first intra substrate connection terminal insulated from the second land just above the first intra substrate connection terminal, and the second group of the second lands include a second inter level connection terminal insulated from the first land just below the second inter level connection terminal, and the first intra substrate connection terminal and the second inter level connection terminal are connected by a bent connection path having a stair-step shape.

11. A first level assembly comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands;

a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a plurality of joint balls disposed on the second lands, respectively;

an upper level mounting base defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed on the fourth surface so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a chip mounting area assigned adjacent to the upper level second lands on the fourth surface, wherein the mounting base is a BGA tape.

12. A first level assembly comprising:

a mounting base defined by a first surface and a second surface opposite to the first surface;

a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands;

a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands;

a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a plurality of joint balls disposed on the second lands, respectively;

an upper level mounting base defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed on the fourth surface so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a chip mounting area assigned adjacent to the upper level second lands on the fourth surface, wherein the upper level semiconductor chip is mounted in a facedown configuration on the chip mounting area.

13. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands, and a plurality of bent connection paths embedded in the mounting base so as to connect the first lands with the second lands; and

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.

14. The second level assembly of claim 13, wherein the mounting base is a BGA tape.

15. The second level assembly of claim 13, wherein the semiconductor chip is mounted in a facedown configuration on the chip mounting area.

16. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface, wherein the second group of the first lands include a first intra substrate connection terminal insulated from the second land just above the first intra substrate connection terminal, and the second group of the second lands include a second inter level connection terminal insulated from the first land just below the second inter level connection terminal, and the first intra substrate connection terminal and the second inter level connection terminal are connected by a bent connection path having a stair-step shape.

17. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface;

a plurality of second connection terminals disposed in a second substrate mounting area assigned adjacent to the substrate mounting area on the packaging pad;

a plurality of second signal terminals disposed around the second substrate mounting area on the first surface of the packaging substrate;

a plurality of second signal wiring connected to the second connection terminals and the second signal terminals;

a plurality of second packaging balls respectively disposed on the second connection terminals;

a second mounting base disposed above the second substrate mounting area so as to lie in the same level of the first mounting base, the second mounting base, the second mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, and a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and

a semiconductor chip mounted on a second chip mounting area assigned on the second mounting base so as to be lie in the same level of the semiconductor chip.

18. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface;

a plurality of joint balls disposed on the second lands respectively on the mounting base;

an upper level mounting base disposed above the mounting base, being defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a upper level chip mounting area assigned adjacent to the upper level second lands on the fourth surface.

19. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface;

a plurality of joint balls disposed on the second lands respectively on the mounting base;

an upper level mounting base disposed above the mounting base, being defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a upper level chip mounting area assigned adjacent to the upper level second lands on the fourth surface, wherein the second group of the first lands include a first intra substrate connection terminal insulated from the second land just above the first intra substrate connection terminal, and the second group of the second lands include a second inter level connection terminal insulated from the first land just below the second inter level connection terminal, and the first intra substrate connection terminal and the second inter level connection terminal are connected by a bent connection path having a stair-step shape.

20. A second level assembly comprising:

a packaging board defined by a first surface assigning a substrate mounting area;

a plurality of connection terminals disposed on the substrate mounting area;

a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board;

a plurality of signal wiring connected to the connection terminals and the signal terminals;

a plurality of packaging balls disposed on the connection terminals, respectively;

a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands;

a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface;

a plurality of joint balls disposed on the second lands respectively on the mounting base;

an upper level mounting base disposed above the mounting base, being defined by a third surface and a fourth surface opposite to the third surface;

a plurality of upper level first lands disposed on the third surface so as to connect with the joint balls, respectively, being classified into first and second groups of the upper level first lands;

a plurality of upper level second lands disposed so as to face to the upper level first lands, respectively, being classified into first and second groups of the upper level second lands;

a plurality of second straight connection paths embedded in the upper level mounting base so as to connect the first group of the upper level first lands with the first group of the upper level second lands just above the first group of the upper level first lands; and

an upper level semiconductor chip disposed in a upper level chip mounting area assigned adjacent to the upper level second lands on the fourth surface, wherein the mounting base is a BGA tape.