System for logic state detection

• US 6,791,479 B2
• Filed: 03/30/2001
• Issued: 09/14/2004
• Est. Priority Date: 03/30/2001
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Inventors: Clark, Charles Thomas, Kraus, Richard Alen
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): DANG, HUNG Q
• Application Number:
  US09/821,977
• Publication Number:
  US 20020140434A1
• Time in Patent Office: 1,264 Days
• Field of Search: 341/26, 341/22, 340/518, 340/644, 340/14.69, 324/522
• US Class Current: 341/26
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A logic state detection system for detecting the state of at least one state changing device includes a scanning circuit and a current detection circuit. The scanning circuit selectively activates at least one output line electrically connected with the at least one state changing device. Current passes through the scanning circuit to the at least one output line that is activated. The current detection circuit determines whether the state changing device is in a conducting or a non-conducting state as a function of the current.

Claims

1. A logic state detection system for detecting the logic state of state changing devices, the logic state detection system comprising:

at least one state changing device; and

a current detection circuit electrically coupled with the at least one state changing device, the current detection circuit operable to provide current and identify the logic state of the at least one state changing device as a function of a threshold current level wherein the current detection circuit comprises an automatic gain control circuit operable to perform voltage compensation to maintain the threshold current level as voltage supplying the current detection circuit varies.

2. The logic state detection system of claim 1, wherein the threshold current level is a magnitude of current that minimizes electromagnetic interference and is indicative of the logic state of the at least one state changing device.

3. The logic state detection system of claim 1, wherein the current detection circuit comprises the automatic gain control circuit, the automatic gain control circuit operable to adjust the threshold current level as a function of a magnitude of current indicative of the logic state of the at least one state changing device.

4. The logic state detection system of claim 1, wherein the threshold current level is temperature compensated.

5. The logic state detection system of claim 1, further comprising a scan block electrically connected with the at least one state changing device, the scan block operable to selectively pass current supplied by the current detection circuit to the at least one state changing device.

6. The logic state detection system of claim 1, further comprising a data processor electrically coupled with the current detection circuit, the data processor operable to adjust the threshold current level as a function of the anticipated magnitude of current provided by the current detection circuit indicative of the logic state of the at least one state changing device.

7. A logic state detection system for detecting the logic state of state changing devices, the logic state detection system comprising:

a scan block electrically coupled with at least one state changing device, the scan block operable to selectively pass current to the at least one state changing device; and

a current detection circuit electrically coupled with the scan block the current detection circuit operable to identify the logic state of the at least one state changing device as a function of the current wherein the current detection circuit comprises a current management circuit and an output driver circuit, the current management circuit operable to provide current to the scan block and monitor the magnitude of current provided.

8. The logic state detection system of claim 7, further comprising a resistor block electrically connected with the scan block and the at least one state changing device, the resistor block operable as a low pass filter.

9. The logic state detection system of claim 8, wherein the resistor block comprises at least one resistor and at least one capacitor.

10. The logic state detection system of claim 7, further comprising a data processor electrically connected with the current detection circuit and the scan block, the data processor operable to direct the scan block to selectively pass current, the data processor also operable to receive indication of the logic state of the at least one state changing device from the current detection circuit.

11. The logic state detection system of claim 10, wherein the data processor comprises a first clock and a second clock, the first clock operable during a setup mode, the second clock operable during a scan mode.

12. The logic state detection system of claim 7, wherein the at least one state changing device is electrically connected between the scan block and a ground connection.

13. A logic state detection system for detecting the logic state of state changing devices, the logic state detection system comprising:

a scanning circuit comprising a plurality of output ports each electrically coupled with a state changing device, the output ports selectively activated during one of a setup mode and a scan mode; and

a current detection circuit electrically coupled with the scanning circuit, the current detection circuit operable to supply current through the output ports during the setup mode and through selectively activated output ports during the scan mode, the current detection circuit operable to provide indication of the logic state of the state changing device as a function of the current during the scan mode.

14. The logic state detection system of claim 13, wherein the scanning circuit comprises a plurality of scan blocks, each of the scan blocks responsive to a serial data stream and an enabling signal to selectively activate the output ports, the serial data stream provided to all the scan blocks and the enabling signal provided exclusively to each of the scan blocks.

15. The logic state detection system of claim 13, wherein current supplied by the current detection circuit during the setup mode is operable to charge a plurality of capacitors electrically coupled with the output ports.

16. The logic state detection system of claim 13, further comprising a data processor electrically coupled with the scanning circuit and the current detection circuit, the data processor operable during the scan mode to obtain the logic state of a plurality of state changing devices as a function of sequential activation and deactivation of each of the output ports.

17. The logic state detection system of claim 16, wherein the data processor comprises a first clock and a second clock, the first clock operable during the setup mode and the second clock operable during the scan mode.

18. The logic state detection system of claim 13, wherein the scanning circuit is operable to sequentially activate all the output ports and then sequentially deactivate all the output ports as a function of a first clock.

19. The logic state detection system of claim 13, wherein the scanning circuit is operable to activate and then deactivate each of the output ports in sequence as a function of a second clock.

20. The logic state detection system of claim 13, wherein the scanning circuit comprises at least two scan blocks, the scan blocks operable in parallel with the current detection circuit.

21. The logic state detection system of claim 13, wherein the scan blocks are selectively disabled as a function of selective activation of the output ports.

22. The logic state detection system of claim 13, wherein the state changing devices are low side ground referenced state changing devices.

23. The logic state detection system of claim 13, wherein the state changing devices are high side state changing devices and the scanning circuit comprises a high side interface circuit electrically connected with the state changing devices.

24. The logic state detection system of claim 13, wherein the scanning circuit comprises a resistor block electrically coupled with each of the output ports, the resistor block operable to limit the current and minimize electromagnetic interference and electrostatic discharge.

25. A logic state detection system for detecting the logic state of a plurality of state changing devices, the logic state detection system comprising:

a plurality of scan blocks electrically coupled with the state changing devices, wherein the scan blocks are operable to selectively pass current to at least one of the state changing devices;

a data processor electrically coupled with the scan blocks, the data processor operable to selectively direct the scan blocks with a serial data stream by selective enablement of each of the scan blocks;

a current detection circuit electrically coupled with the scan blocks and the first data processor, the current detection circuit operable to monitor the current passed by the scan blocks and indicate the logic state of the state changing devices as a function of a threshold current level; and

a high side interface circuit electrically connected with the scan blocks and the state changing devices, wherein the high side interface device is operable to provide an interface for state changing devices configured as high side state changing devices.

26. The logic state detection system of claim 25, further comprising a resistor block electrically connected with the scan blocks and the state changing devices, wherein the resistor block is operable as a low pass filter.

27. The logic state detection system of claim 25, wherein the state changing devices are operable to selectively assume at least two impedance levels, the data processor operable to modify the threshold current level as a function of current indicative of one of the impedance levels.

28. The logic state detection system of claim 25, wherein the current detection circuit comprises a current management circuit and an output driver circuit.

29. The logic state detection system of claim 28, wherein the current management circuit is operable to differentiate between a non-conducting state changing device and a conducting state changing device.

30. The logic state detection system of claim 28, wherein the output driver circuit is operable to generate signals provided to the data processor indicative of a non-conducting state changing device and a conducting state changing device.

31. A method of determining the logic state of a plurality of state changing devices, the method comprising:

selectively activating one of a plurality of output lines, the output lines each electrically connected with at least one of the state changing devices;

passing current to the activated one of the output lines; and

indicating the logic state of the at least one of the state changing devices as a function of the current

entering a setup mode;

activating all of the output lines;

passing current to the output lines to charge a plurality of capacitors; and

deactivating all the output lines.

32. The method of claim 31, further comprising the initial act of entering a scan mode.

33. The method of claim 31, wherein selectively activating one of the output lines comprises:

transmitting a serial data stream to a plurality of scan blocks;

transmitting an enabling signal to one of the scan blocks; and

responding to the serial data stream with one of the scan blocks as a function of the enabling signal.

34. The method of claim 31, wherein passing current to the activated one of the output lines comprises maintaining current flow that minimizes electromagnetic interference.

35. The method of claim 31, wherein indicating the logic state of the one of the state changing devices comprises:

monitoring the current magnitude; and

providing a signal indicative of the current magnitude with respect to a threshold current level.

36. The method of claim 31, wherein indicating the logic state of the one of the state changing devices comprises temperature compensating to accurately monitor the current.

37. The method of claim 31, wherein indicating the logic state of the one of the state changing devices comprises voltage compensating to accurately monitor the current.

38. The method of claim 31, wherein indicating the logic state of the one of the state changing devices comprises selecting a threshold current level as a function of the anticipated current indicative of the logic state of the at least one state changing device.

39. A method of determining the logic state of a plurality of state changing devices, the method comprising:

selectively activating one of a plurality of output lines, the output lines each electrically connected with at least one of the state changing devices passing current to the activated one of the output lines;

indicating the logic state of the at least one of the state changing devices as a function of the current;

transmitting a serial data stream to a plurality of scan blocks;

transmitting an enabling signal to one of the scan blocks; and

responding to the serial data stream with one of the scan blocks as a function of the enabling signal.