I/O node for a computer system including an integrated graphics engine

• US 6,791,554 B1
• Filed: 12/27/2001
• Issued: 09/14/2004
• Est. Priority Date: 12/27/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hewitt, Larry D., Gulick, Dale E., Mergard, James
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US10/034,560
• Time in Patent Office: 992 Days
• Field of Search: 345/519, 345/501, 345/520, 345/559, 345/530, 710/52, 710/306, 710/305
• US Class Current: 345/519
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

Claims

1. An input/output node for a computer system, said input/output node comprising:

a first transceiver unit implemented on an integrated circuit chip, wherein said first transceiver unit is configured to receive first packet transactions and to transmit second packet transactions on a first link of a packet bus;

a second transceiver unit implemented on said integrated circuit chip, wherein said second transceiver unit is coupled to receive said second packet transactions and to transmit said first packet transactions on a second link of said packet bus;

a packet tunnel implemented on said integrated circuit chip, wherein said packet tunnel is coupled to convey selected ones of said first and said second packet transactions between said first transceiver unit and said second transceiver unit;

a graphics engine implemented on said integrated circuit chip, wherein said graphics engine is coupled to receive graphics packet transactions from said first transceiver unit and is configured to render digital image information in response to receiving said graphics packet transactions; and

a graphics interface implemented on said integrated circuit chip, wherein said graphics interface is coupled to receive additional graphics packet transactions from said first transceiver unit and configured to translate said additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

2. The input/output node as recited in claim 1 further comprising a control unit implemented on said integrated circuit chip, wherein said control unit is coupled to control the conveyance of said selected ones of said first and said second packet transactions, said graphics packet transactions and said additional graphics packet transactions between said first transceiver unit and said second transceiver unit, between said first transceiver unit and said graphics engine and between said first transceiver unit and said graphics interface, respectively.

3. The input/output node as recited in claim 2, wherein said graphics engine is further configured to translate said digital image information into packet transactions suitable for transmission upon said first link of said packet bus.

4. The input/output node as recited in claim 3, wherein said graphics engine is further configured to receive said graphics packet transactions through said packet tunnel.

5. The input/output node as recited in claim 4, wherein said graphics engine further includes a configuration register, wherein said configuration register provides a user selectable bit for enabling and disabling said graphics engine.

6. The input/output node as recited in claim 5, wherein said graphics engine is further configured to provide signals corresponding to said digital image information for display.

7. The input/output node as recited in claim 6, wherein said graphics interface is further configured to receive said additional graphics packet transactions through said packet tunnel.

8. A computer system comprising:

a processor;

a packet bus including a first link and a second link, wherein said first link is coupled to said processor; and

an input/output node coupled to said first link and to said second link, said input/output node including;

a first transceiver unit implemented on an integrated circuit chip, wherein said first transceiver unit is configured to receive first packet transactions and to transmit second packet transactions on said first link of said packet bus;

a second transceiver unit implemented on said integrated circuit chip, wherein said second transceiver unit is coupled to receive said second packet transactions and to transmit said first packet transactions on said second link of said packet bus;

a packet tunnel implemented on said integrated circuit chip, wherein said packet tunnel is coupled to convey selected ones of said first and said second packet transactions between said first transceiver unit and said second transceiver unit;

a graphics engine implemented on said integrated circuit chip, wherein said graphics engine is coupled to receive graphics packet transactions from said first transceiver unit and is configured to render digital image information in response to receiving said graphics packet transactions; and

a graphics interface implemented on said integrated circuit chip, wherein said graphics interface is coupled to receive additional graphics packet transactions from said first transceiver unit and configured to translate said additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

9. The computer system as recited in claim 8, wherein said I/O node further includes a control unit implemented on said integrated circuit chip, wherein said control unit is coupled to control the conveyance of said selected ones of said first and said second packet transactions, said graphics packet transactions and said additional graphics packet transactions between said first transceiver unit and said second transceiver unit, between said first transceiver unit and said graphics engine and between said first transceiver unit and said graphics interface, respectively.

10. The computer system as recited in claim 9, wherein said graphics engine is further configured to translate said digital image information into packet transactions suitable for transmission upon said first link of said packet bus.

11. The computer system as recited in claim 10, wherein said graphics engine is further configured to receive said graphics packet transactions through said packet tunnel.

12. The computer system as recited in claim 11, wherein said graphics engine further includes a configuration register, wherein said configuration register provides a user selectable bit for enabling and disabling said graphics engine.

13. The computer system as recited in claim 12, wherein said graphics engine is further configured to provide signals corresponding to said digital image information for display.

14. The computer system as recited in claim 13, wherein said graphics interface is further configured to receive said additional graphics packet transactions through said packet tunnel.

15. The computer system as recited in claim 14, wherein said packet bus is a point-to-point link compatible with HyperTransport™

technology.

16. An input/output node for a computer system, said input/output node comprising:

a first transceiver unit implemented on an integrated circuit chip, wherein said first transceiver unit is configured to receive first packet transactions and to transmit second packet transactions on a first link of a packet bus;

a second transceiver unit implemented on said integrated circuit chip, wherein said second transceiver unit is coupled to receive said second packet transactions and to transmit said first packet transactions on a second link of said packet bus;

a packet tunnel implemented on said integrated circuit chip, wherein said packet tunnel is coupled to convey selected ones of said first and said second packet transactions between said first transceiver unit and said second transceiver unit;

a graphics interface implemented on said integrated circuit chip, wherein said graphics interface is coupled to receive graphics packet transactions from said first transceiver unit and configured to translate said graphics packet transactions into graphics transactions suitable for transmission upon a graphics bus; and

a graphics engine implemented on said integrated circuit chip, wherein said graphics engine is coupled to said graphics bus and configured to receive said graphics transactions from said graphics interface.

17. The input/output node as recited in claim 16 further comprising a control unit implemented on said integrated circuit chip, wherein said control unit is coupled to control the conveyance of said selected ones of said first and said second packet transactions and said graphics packet transactions between said first transceiver unit and said second transceiver unit and between said first transceiver unit and said graphics interface, respectively.

18. The input/output node as recited in claim 17, wherein said graphics engine is further configured to render digital image information in response to receiving said graphics transactions from said graphics interface.

19. The input/output node as recited in claim 18, wherein said graphics engine is further configured to translate said digital image information into graphics transactions suitable for transmission upon said graphics bus.

20. The input/output node as recited in claim 19, wherein said graphics engine further includes a configuration register, wherein said configuration register provides a user selectable bit for enabling and disabling said graphics engines.

21. The input/output node as recited in claim 20, wherein said graphics engine is further configured to provide signals corresponding to said digital image information for display.

22. The input/output node as recited in claim 21, wherein said graphics interface is further configured to receive said graphics packet transactions through said packet tunnel.

23. A computer system comprising:

a processor;

a packet bus including a first link and a second link, wherein said first link is coupled to said processor; and

an input/output node coupled to said first link and to said second link, said input/output node including;

a first transceiver unit implemented on an integrated circuit chip, wherein said first transceiver unit is configured to receive first packet transactions and to transmit second packet transactions on said first link of said packet bus;

a second transceiver unit implemented on said integrated circuit chip, wherein said second transceiver unit is coupled to receive said second packet transactions and to transmit said first packet transactions on said second link of said packet bus;

a packet tunnel implemented on said integrated circuit chip, wherein said packet tunnel is coupled to convey selected ones of said first and said second packet transactions between said first transceiver unit and said second transceiver unit;

a graphics interface implemented on said integrated circuit chip, wherein said graphics interface is coupled to receive graphics packet transactions from said first transceiver unit and configured to translate said graphics packet transactions into graphics transactions suitable for transmission upon a graphics bus; and

a graphics engine implemented on said integrated circuit chip, wherein said graphics engine is coupled to said graphics bus and configured to receive said graphics transactions from said graphics interface.

24. The computer system as recited in claim 23, wherein said I/O node further includes a control unit implemented on said integrated circuit chip, wherein said control unit is coupled to control the conveyance of said selected ones of said first and said second packet transactions and said graphics packet transactions between said first transceiver unit and said second transceiver unit and between said first transceiver unit and said graphics interface, respectively.

25. The computer system as recited in claim 24, wherein said graphics engine is further configured to render digital image information in response to receiving said graphics transactions from said graphics interface and to translate said digital image information into graphics transactions suitable for transmission upon said graphics bus.

26. The computer system as recited in claim 25, wherein said graphics engine further includes a configuration register, wherein said configuration register provides a user selectable bit for enabling and disabling said graphics engines.

27. The input/output node as recited in claim 26, wherein said graphics interface is further configured to receive said graphics packet transactions through said packet tunnel.