Multichannel, multimode DOCSIS headend receiver

• US 6,791,995 B1
• Filed: 06/13/2002
• Issued: 09/14/2004
• Est. Priority Date: 06/13/2002
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Terayon Communications Systems Incorporated (Motorola Solutions, Inc.)
• Inventors: Azenkot, Yehuda, Rakib, Selim Shlomo
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Swickhamer, Christopher M
• Application Number:
  US10/172,035
• Time in Patent Office: 824 Days
• Field of Search: 370/389, 370/391, 370/392, 370/401, 370/412, 370/414, 370/416, 370/434, 370/441, 370/442, 370/458, 370/461, 370/486, 370/538, 370/436, 370/447, 370/426, 725/111, 725/114, 725/121, 725/124, 725/138, 725/144, 725/117, 375/229-236, 375/341, 375/346
• US Class Current: 370/436
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/709709 Methods of preventing interference
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04N 21/239 Interfacing the upstream path of the transmission network, e.g. prioritizing client content requests hybrid fiber coaxial [HFC] networks for upstream channel allocation for video distribution H04L12/2801; flow control in data networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/643 Communication protocols network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP], H04L65/65
• CPC Class Codes: H04N 21/64723 Monitoring of network processes or resources, e.g. monitoring of network load traffic related reporting in data switching networks H04L43/062
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A multichannel, mixed mode cable modem termination system receiver capable of receiving multiple channels of digital data transmitted on one or more hybrid fiber coaxial cable systems, each the channels being either single mode or mixed-mode. Mixed mode channels are time division multiplexed and have overlapping bandwidth and each sub-channel of a mixed mode channel can have a different center frequency, symbol rate and/or multiplexing type. The receiver is comprised of a plurality of analog front end circuits coupled to the various HFC systems, each selective coupled to any one of a plurality of digital front end receivers. Control circuitry controls these circuits to receive multiple mixed-mode or single mode channels, simultaneously if necessary. An arbiter decides which bursts get processed first in a back end shared demodulator which recovers the data from each burst. The preferred shared demodulator includes an equalizer, predictor and rotational amplifier which processes both TDMA and SCDMA data bursts post despreader to reduce reception data errors.

Claims

1. A head end receiver for a distributed system of digital data transceivers coupled to said head end receiver by a plurality of hybrid fiber coaxial cable (hereafter HFC) systems, comprising:

a plurality of channel receivers, each coupled to one or more of said HFC systems, and each capable of receiving mixed mode upstream bursts in different sub-channels that have overlapping bandwidth but which are multiplexed in time, where each subchannel burst may have a different symbol rate, different RF frequency, different multiplexing type and different Synchronous Code Division Multiple Access (hereafter SCDMA) frame size;

a shared back end demodulator circuit for recovering the data from each burst, making measurements and calculations on at least some bursts transmitted by each cable modem which are sent down to the cable modem which sent said burst which are useful in establishing at least frame boundary and minislot boundary synchronization and upstream equalization;

an arbiter coupled to receive the burst data output by each said channel receiver and structured to supply received data to said shared back end circuit such that said shared back end circuit is shared so as to process all data from all said channel receivers at different times;

control circuitry for controlling at least said plurality of channel receivers and said shared back end circuit to provide multichannel, mixed-mode reception of digital data.

2. The apparatus of claim 1 wherein each of said plurality of channel receivers is comprised of an analog front end circuit each of which performs wideband analog-to-digital sampling and is coupled to an HFC system, and a digital front end receiver circuit coupled to all said analog front end circuits via a multiplexer, said digital front end circuit functioning to mix the samples received from a selected one of said analog front end circuits down to baseband and performs narrow band noise excision.

3. The apparatus of claim 2 wherein each digital front end circuit includes a multiplexer having a plurality of inputs, each input coupled to the output of one of said analog front end circuits and having an output that couples the digital samples on a selected one of said inputs to the rest of the circuitry of said digital front end receiver circuit for processing, and having a select control input coupled to said control circuitry for receiving a control signal controlling which input of said multiplexer is coupled to said output.

4. The apparatus of claim 2 wherein said control circuitry comprises:

a plurality of control registers;

a state machine having inputs coupled to said plurality of control registers, said state machine having control signal outputs coupled to said plurality of channel receivers;

a microprocessor coupled to load data into said control registers and controlled by a media access control process to generate the proper data to load into said control registers to cause said state machine to generate appropriate control signals to receive the data of a channel or to load control data into control registers of various circuits in a channel receiver to control those circuits to receive separate logical channels of a mixed mode channel and to generate a switch signal at an appropriate time to cause the various circuits of said channel receiver to switch from use of control data controlling the circuits to properly process the data of a first sub-channel of a mixed mode channel to use of other control data controlling the circuits to properly process the data of a second sub-channel of a mixed mode channel.

5. The apparatus of claim 4 wherein said microprocessor is programmed to control said control circuitry to carry out the following steps:

determine an expected burst type and time of arrival of an expected burst on a channel to be received from data in upstream channel descriptor and MAP messages and determine how much time is left before the burst arrives from an appropriate upstream minislot counter assigned to the hybrid fiber coaxial cable system on which the burst is scheduled for transmission;

select an available digital front end receiver circuit to receive an expected burst, and send a select control signal to said multiplexer in said selected digital front end receiver circuit to cause coupling thereof to one of said analog front end circuits which is coupled to an HFC system on which said expected burst will be transmitted;

load frequency control data into one or more registers of a direct digital frequency synthesizer, each said register storing data that controls the frequency of a local oscillator signal generated by said direct digital frequency synthesizer during reception of a burst on a sub-channel to which said register is assigned, said sub-channel being the channel itself if said channel is not mixed mode, and being one of two or more sub-channels if said channel is mixed mode;

load symbol rate data into one or more registers of an interpolator and a variable decimator, each said register storing data that defines a symbol rate during reception of a burst on a sub-channel to which said register is assigned, said sub-channel being the channel itself if said channel is not mixed mode, and being one of two or more sub-channels if said channel is mixed mode;

send a control signal to turn on or turn off a narrow band noise excision circuit;

send a TDMA/SCDMA control data to load one or more registers in at least a despreader circuit, each register storing control data controlling whether said despreader despreads the data of a burst received on a sub-channel to which said register is assigned and defining the symbol rate of said burst, said sub-channel being the channel itself if said channel is not mixed mode, and being one of two or more sub-channels if said channel is mixed mode;

prepend burst parameter data from at least said upstream channel descriptor (hereafter UCD) message data that pertains to a burst into a front end buffer of said digital front end receiver circuit to the memory locations where the burst data of the expected burst will be stored; and

determining from MAP message data pertaining to the expected burst the minislot count when the burst will start to arrive and terminate and determining from the upstream minislot counter which is counting upstream minislot counts for the HFC system on which the burst is arriving when a guard band between sub-channels of the mixed-mode channel being received is occurring, and sending a switch signal to all circuits in said digital front end receiver which have been loaded with data controlling operations by said circuits for two or more sub-channels causing said circuits to switch to using control data in a register assigned to a sub-channel to be received at the end of the said guard band.

6. The apparatus of claim 5 wherein said microprocessor is further programmed to control said control circuitry to send data as part of said TDMA/SCDMA control data which indicates the location of code 0 in SCDMA sub-channel frames.

7. The apparatus of claim 1 wherein said control circuitry includes a computer programmed to implement a separate media access control process for each sub-channel that said receiver can receive.

8. The apparatus of claim 1 wherein each said channel receiver includes a front end buffer for storing sample and other data, and wherein said control circuitry includes a computer programmed to prepend burst parameter data for each burst to be processed by a channel receiver into the front end buffer of said channel receiver such that said burst parameter data precedes the burst data and travels with the burst data on the same data path through said shared back end demodulator circuit, said burst parameter data controlling and configuring circuits in said back end demodulator to properly process said burst data.

9. The apparatus of claim 1 wherein each said channel receiver includes an analog front end circuit having an output, and a digital front end receiver circuit which comprises:

a multiplexer having multiple inputs, each input coupled to an output of a different front end circuit, and a select control input coupled to said control circuitry and having an output;

a digital mixer having an input coupled to said output of said multiplexer and having an output and having a local oscillator signal input for mixing the signal for each sub-channel to be received down to baseband;

a direct digital frequency synthesizer for generating a local oscillator signal at a center frequency of each sub-channel to be received when data from said subchannel is being received, and having an input coupled to said control circuitry for receiving frequency control data and having an input coupled to said control circuitry for receiving a switch signal and having a plurality of registers therein, each for storing frequency control data that controls the frequency of the signal generated by said direct digital frequency synthesizer when receiving one sub-channel;

an interpolator for resampling the data of each subchannel at a symbol clock rate of that sub-channel, and having a symbol rate input coupled to said control circuitry and a switch signal input coupled to said control circuitry for receiving a switch signal indicating when to switch from processing the data of one sub-channel to processing data of another sub-channel, said symbol rate input for receiving symbol rate data from said control circuitry for multiple sub-channels, and having a plurality of registers, each for storing symbol rate input for one sub-channel to be received;

a variable decimator for reducing the sample rate of the baseband data stream of a sub-channel burst being received to two samples per symbol based upon the symbol rate of the burst, and having a symbol rate input coupled to said control circuitry and a switch signal input coupled to said control circuitry for receiving a switch signal indicating when to switch from processing the data of one sub-channel to processing data of another sub-channel, said symbol rate input for receiving symbol rate data from said control circuitry for multiple sub-channels, and having a plurality of registers, each for storing symbol rate input for one sub-channel to be received;

a narrow band excision circuit for analyzing the spectrum of each sub-channel and determining if narrow band interference exists, and, if so, setting coefficients of a digital notch filter to suppress said narrow band interference and adapt said coefficients to best suppress said narrow band interference, and having a switch signal input coupled to said control circuitry for receiving a switch signal indicating when to switch from processing the data of one sub-channel to processing data of another sub-channel;

an impulse detector for detecting impulse noise and marking affected samples with an indication that the sample may be corrupted by impulse noise by opening a window in time and measuring a signal power received during said window and comparing the measured signal power to an expected power level to make a determination whether excessive impulse noise power is present, and, if present, marking all samples taken during said window with an erasure bit;

a despreader circuit for despreading the spectrum of synchronous code division multiple access bursts, and having an input coupled to said control circuitry for receiving data indicating whether the bursts in each sub-channel are spread spectrum or not, and having a switch control input coupled to said control circuitry for receiving a switch signal indicating when to switch between processing the data of a first sub-channel and processing the data of a second sub-channel; and

a front end buffer having an input coupled to receive data from said despreader and having an input coupled to said control circuitry for receiving burst parameter data to prepend to burst data, said burst parameter data for controlling circuitry of said shared back end demodulator circuit.

10. A process for multichannel, mixed-mode reception of digital data transmissions at a cable modem termination system (hereafter CMTS) receiver coupled via a plurality of hybrid fiber coaxial (hereafter HFC) cable systems to a plurality of DOCSIS compliant, asynchronous time division multiple access and synchronous code division multiple access cable modems, said CMTS receiver comprising a plurality of channel receivers coupled to a plurality of HFC systems, each channel receiver comprising a plurality of analog front end circuits, each coupled to one of said plurality of HFC systems and each coupled through multiplexers to any one of a plurality of digital front end receivers, each said digital front end receiver coupled via a front end buffer and an arbiter to a shared back end demodulator and coupled to control circuitry, said process comprising the steps:

(1) using upstream channel descriptor message data and MAP message data to determine when a burst on a channel will be transmitted and whether the channel is or is not mixed mode;

(2) selecting an available digital front end receiver to receive said burst and sending control data to circuitry in said digital front end receiver to configure it to be coupled to the analog front end circuit coupled to the HFC system on which the burst will be transmitted and to configure said digital front end receiver to receive each sub-channel burst in said channel (hereafter sub-channel burst refers to the channel burst if the channel is not mixed-mode);

(3) loading burst parameter data and channel parameter data pertaining to each expected sub-channel burst in a front end buffer of said selected digital front end receiver in a position to prepend the data of said sub-channel burst when that data is received;

(4) filtering out unwanted radio frequency signals from the HFC system on which the burst is arriving and wide band sampling said burst or bursts from each sub-channel;

(5) mixing each sub-channel burst down to baseband during the time the burst from that sub-channel is being received;

(6) resampling each sub-channel burst at a multiple of a symbol clock rate of the burst;

(7) filtering and decimating each sub-channel burst down to a sample rate of some predetermined number of samples per symbol based upon the symbol rate of each sub-channel burst;

(8) performing a narrow band excision to remove or suppress narrow band noise;

(9) writing burst parameter data and carrier phase and amplitude error correction factors pertaining to a particular sub-channel burst into a front end buffer to prepend the burst data of the burst;

(10) writing the burst data of each sub-channel burst into a front end buffer that has the burst parameter data and error correction factors pertaining to the burst;

(11) providing multichannel capability by repeating steps 1 through 10 for bursts scheduled on any of the HFC cable systems to which said CMTS receiver is connected using other available digital front end receivers of said CMTS receiver;

(12) arbitrating among the collection of data from bursts already received and stored in the front end buffers of said digital front end receivers, and supplying said burst data and burst parameter data and error correction factors to said shared back end demodulator according to a priority scheme established by said arbitration; and

(13) recovering the data of every burst using said shared back end demodulator.

11. The process of claim 10 wherein said step of filtering and decimating is carried out in a manner such that the same delay occurs as each burst is processed by this step regardless of the symbol rate of the burst.

12. The process of claim 11 wherein said step of filtering and decimating is carried out by passing each burst through a conventional decimator and a variable delay element which has its delay set based upon the symbol rate.

13. The process of claim 11 wherein said step of filtering and decimating is carried out by passing each burst through a conventional decimator, and, when bursts in different sub-channels have different symbol rates, causing a ranging process to be carried out by the cable modem that is scheduled to send the next sub-channel burst to cause the cable modem scheduled to send the next sub-channel burst to adjust its ranging delay such that given the delay imposed by said conventional decimator, the burst from said cable modem arrives at a shared back end demodulator circuit aligned in time with minislot boundaries of a minislot for which the burst was scheduled.

14. The process of claim 11 wherein said step of filtering and decimating is carried out by passing the burst from each sub-channel through a conventional decimator and, when there is a shift in symbol rate between a first sub-channel burst and a second sub-channel burst on a mixed mode channel, shifting the timebase symbol clock for the hybrid fiber coaxial cable system on which the second sub-channel burst is scheduled so as to compensate for the changed delay in said conventional decimator caused by the different symbol rate.

15. The process of claim 10 wherein step 13 further comprises the steps:

(A) despreading the spectrum of any synchronous code division multiplexed bursts, and if the burst is not synchronous code division multiple access (hereafter SCDMA) multiplexed, passing the sample data through or around a despreader circuit without alteration;

(B) performing impulse noise detection by opening a window in time and measuring a received signal power during said window and comparing said received signal power to an expected power level, and, if the comparison indicates impulse noise was probably present during said window, marking any symbols that were received during said window and which may be corrupted by impulse noise with an erasure bit;

(C) measuring the start of burst time of at least ranging bursts and reporting any synchronization errors to assist each cable modem in achieving for its bursts minislot and kiloframe boundary alignment at the CMTS receiver so as to achieve upstream synchronization;

(D) recovering a symbol clock on at least time division multiple access data and ranging bursts and resampling TDMA and SCDMA burst symbol data at the correct timing using the recovered symbol clock and storing the re-sampled data in a frame buffer;

(E) processing a unique word preamble of each sub-channel burst to develop initial phase and amplitude error correction factors and using said initial phase and amplitude error correction factors to track and correct phase and amplitude errors in preamble symbols of each burst and storing the corrected preamble symbols in an equalizer buffer, and using said phase and amplitude error correction factors to track and correct phase and amplitude errors in the data symbols of said sub-channel burst and storing corrected data symbols in a burst buffer;

(F) processing said corrected preamble symbols of each sub-channel burst to develop upstream equalization coefficients for the cable modem which transmitted said burst and sending said upstream equalization coefficients to said cable modem which transmitted said sub-channel burst in a downstream message for use in updating tap coefficients in an upstream equalization filter;

(G) processing the data symbols of each interleaved burst to deinterleave them;

(H) decoding the data symbols of each burst in a manner appropriate to the type of encoding used to encode data bits into the burst'"'"'s data symbols to recover said data bits;

(I) reinterleaving uncoded bits output from step H for Trellis Code Modulated (hereafter TCM) bursts;

(J) for TCM bursts, receiving the coded bits from step H and the deinterleaved uncoded bits from step I and degrouping them back into a Reed-Solomon code word byte stream;

(K) descrambling the Reed-Solomon code word byte stream for bursts that are scrambled;

(L) de-interleaving the Reed-Solomon code word byte stream of TDMA bursts;

(M) error correcting the Reed-Solomon code words to generate and output recovered data bits transmitted by the cable modem that transmitted the burst.

16. The process of claim 15 wherein step D further comprises receiving an initial symbol clock offset value from the start of burst detection performed in step C and using that initial value as a starting point to recover and track the symbol clock of each burst.

17. The process of claim 16 wherein step D further comprises the step of using the recovered symbol clock to resample the symbol data at the correct timing and output a predetermined number of re-timed samples per symbol.

18. The process of claim 16 wherein step C start of burst detection includes a correlation step to measure carrier offset, and wherein samples that are marked with an erasure bit are not used or ignored in said correlation step.

19. The process of claim 16 wherein step D timing recovery does not use symbols marked as erased in symbol clock recovery.

20. The process of claim 15 wherein tracking loops which accomplish step E do not use symbols which have been marked as erased in step B in tracking and correcting phase and amplitude errors in preamble symbols and data symbols of bursts.

21. The process of claim 15 wherein the process of step F of developing equalization coefficients does not use symbols which have been marked as erased in step B to update tap coefficients.

22. The process of claim 15 further comprising the step of processing both time division multiplexed data bursts as well as spread spectrum data bursts using a equalizer and predictor circuit which cooperates with a rotational amplifier, said equalizer and predictor circuits being finite impulse response digital filters the coefficients and states of which are controlled in a predetermined manner at the beginning of each new spreading interval during reception of spread spectrum data bursts to reduce errors in reception of said data bursts transmitted by a cable modem after said upstream equalization coefficients have been developed and transmitted to said cable modem.

23. The process of claim 15 wherein step H is performed using a Viterbi decoder to decode each Trellis Code Modulated (hereafter TCM) data symbol into the coded and uncoded bits which were encoded into it, and, when the burst is not TCM encoded, using a conventional slicer to decode the data symbols.

24. The process of claim 15 wherein the development of upstream equalization coefficients in step F comprises developing coarse equalization tap coefficients during an initial pass of preamble symbols of training bursts through an adaptive equalization filter followed by fine tuning of said equalization tap coefficients by repeatedly passing at least said preamble symbols of each burst through said adaptive equalization filter using said coarse equalization coefficients as starting tap coefficient values.

25. The process of claim 15 wherein step H is performed using a Viterbi decoder to decode each Trellis Code Modulated (hereafter TCM) data symbol into the coded and uncoded bits which were encoded into it, and, when the burst is not TCM encoded, using a conventional slicer to decode the data symbols, and wherein said Viterbi decoder receives symbols with erasure bits set by an impulse detector which implements step B, and wherein said erasure bit indication for each symbol is used to set branch metric clipping values small when the state of said erasure bit indicates the presence of impulse noise and is used to set branch metric clipping values larger when the state of said erasure bit indicate impulse noise is not present, and wherein said Viterbi decoder outputs the coded and uncoded bits of each constellation point with an erasure indication indicating a level of confidence of the Viterbi decoder in its decision.

26. The process of claim 25 further comprising a step of outputting the number of bytes marked with erasure indications by said Viterbi decoder for use in setting the number of Reed-Solomon information bytes in a Reed-Solomon codeword of future bursts.

27. The process of claim 25 wherein the Reed-Solomon decoding step M uses said erasure bits output by said Viterbi decoder to increase the error detection and correction capability of the Reed-Solomon decoding step.

28. A head end receiver apparatus for multichannel, mixed mode reception of digital data in a distributed system, comprising:

a plurality of analog front end means, each coupled to one of a plurality of hybrid fiber coaxial (hereafter HFC) cable systems, each said system coupled to a plurality of cable modems that transmit DOCSIS 1.x, ATDMA or SCDMA bursts, for filtering out unwanted radio frequency signals and wideband sampling of burst signals on a channel which may have two or more sub-channels transmitting bursts of different center frequency, symbol rate and/or multiplexing type;

a plurality digital front end receiver means, each capable of being selectively coupled to any one of said analog front end means, each digital front end receiver circuit for receiving a select control signal and coupling itself to one of said analog front end means and receiving samples therefrom, mixing the samples of each channel or sub-channel burst received from said selected analog front end means down to baseband, resampling the sample data of each burst at a multiple of the symbol rate of said burst, filtering and decimating each sub-channel burst down to a predetermined number of samples per symbol based upon the symbol rate of the burst, performing narrow band excision to remove or suppress narrow band noise, writing burst parameter data pertaining to the burst being received and phase and amplitude error correction factors pertinent to the burst being received into a front end buffer to prepend the burst data or act as a header for said burst data, and writing the preamble and data symbols of the burst being received into said front end buffer;

a control means coupled to at least said plurality of digital front end receiver means for controlling said digital front end receiver means to receive multiple channels of data from one or more of said HFC systems, each channel being either mixed mode or single mode;

arbitrator means coupled to the front end buffer of each of said plurality of digital front end receiver means, for selecting burst data to be further processed according to a priority scheme, and providing said burst data at an output;

a shared demodulator coupled to receive each burst'"'"'s preamble and data symbols when selected by said arbitrator means and for recovering the data encoded in said data symbols and making predetermined measurements to support ranging by the cable modem and developing phase and amplitude error correction factors for each cable modem from preamble symbols transmitted by said cable modem and using said phase and amplitude error factors developed for each cable modem to correct phase and amplitude errors in bursts transmitted from said cable modem, and developing upstream equalization coefficients from the preamble symbols of at least some bursts for sending to the cable modem which transmitted said burst;

and further comprising equalizer means for processing both time division multiplexed data bursts and code division multiplexed data bursts after despreading to reduce echoes and other noise and use phase and amplitude error correction factors developed for the cable modem which transmitted said data burst to correct for phase and amplitude offset errors in said burst.

29. A head end receiver apparatus for multichannel, mixed mode reception of digital data in a distributed system, comprising:

a plurality of channel receivers, each capable of receiving single mode or mixed-mode channels, each having a front end buffer;

an arbiter coupled to the front end buffers of all said channel receivers for supplying burst data of various bursts on the basis of a priority scheme;

a back end demodulator coupled to receive burst data from said aribiter and recover payload data encoded into each burst; and

a control circuit coupled to control said plurality of channel receivers to receive and process multiple single mode or mixed-mode channels simultaneously if necessary.

30. A process for receiving digital data in a central modem coupled to a plurality of remote modems via a shared transmission medium, comprising:

using a counter to establish upstream minislot boundaries;

assigning minislots for particular bursts and assigning burst parameters that define the type of burst to be transmitted during said assigned minislots and transmitting said assigned minislots and burst parameters to a remote modem which has requested bandwidth;

receiving radio frequency carrier signals and filtering out unwanted radio frequency signals and digitally sampling one or more desired radio frequency carriers modulated with bursts of symbols that encode digital data to generate a sample stream representing a desired channel;

mixing said sample stream down to baseband, and excising narrow band noise;

filtering in a matched filter to improve the signal to noise ratio;

despreading the spectrum of any bursts that are code division multiplexed;

detecting the start of each burst by detecting a unique word preamble, and measuring a time offset between an actual start time and an anticipated start time and using said time offset to send a message to a remote modem which transmitted said burst to assist said remote modem in ranging to achieve minislot synchronization so that said remote modem'"'"'s bursts can be timed to arrive at said central modem aligned in time with the minislot boundaries assigned to said transmission;

recovering a carrier frequency of each burst;

recovering the symbol clock of each time division multiplexed burst;

processing a preamble portion of each burst to generate phase and amplitude correction factors unique to the remote modem which transmitted said burst and using said phase and amplitude correction factors developed for a particular remote modem to correct phase and amplitude offset errors of the data portion of a burst from said remote modem;

processing a preamble portion of each burst in an equalizer to develop upstream equalization coefficients for the remote modem which transmitted said burst, and transmitting said upstream equalization coefficients to said remote modem for its use in adjusting the tap coefficients of a preemphasis filter therein used to filter upstream transmissions to said central modem;

filtering time division multiplexed bursts using the same equalizer used to generate said upstream equalization coefficients to remove echoes and using a predictor to remove further noise, and outputting filtered symbols;

filtering bursts of symbols that have been code division multiplexed using cyclic, orthogonal spreading codes using the same equalizer used to develop said upstream equalization coefficients to remove echoes and using a predictor digital filter to remove further noise, and setting state and tap coefficients of said equalizer and predictor digital filters to a new state at the beginning of each spreading interval, said new state determined according to a predetermined algorithm designed to make use of the property that echoes of chips within the same spreading interval will appear in different, predictable codes than the symbol data encoded in said chips in a code domain after despreading when the spectrum was spread using cyclic, orthogonal spreading codes, and outputting filtered symbols;

detecting and error correcting the digital data encoded in said filtered symbols.

31. A process for filtering symbols of time division multiplexed bursts and symbols of code division multiplexed bursts after despreading using a same equalizer filter, comprising the steps:

receiving noise corrupted symbols of time division multiplexed bursts and receiving noise corrupted chips of synchronous code division multiplexed (SCDMA) bursts which have had their spectra spread using cyclic, orthogonal spreading codes, and bypassing a despreading step for said time division multiplexed bursts while processing said received, noise corrupted chips of said SCDMA bursts with a despreader to recover noise corrupted symbols therefrom, each of said time division multiplexed and SCDMA bursts having been filtered in a transmitter which transmitted said burst using a pre-emphasis filter having its tap coefficients set to equalize the channel through which the burst was transmitted;

filtering said noise corrupted symbols of said time division multiplexed bursts using a digital equalizer filter to remove echoes and summing the resulting filtered symbols with the output of a digital predictor filter to remove further noise, and outputting filtered symbols from said time division multiplexed bursts;

filtering said noise corrupted symbols output by said despreading step using the same digital equalizer filter used to filter said noise corrupted symbols of said time division multiplexed bursts to remove echoes and summing the resulting filtered symbols with the output of the same digital predictor digital filter to remove further noise, and controlling the states and coefficients said digital equalizer filter and said digital predictor filter according to any algorithm designed to make use of the property that echoes of chips within the same spreading interval will appear in different, predictable codes than the symbol data encoded in said chips in the code domain after despreading if the spectrum of the spread spectrum burst being processed was spread using cyclic, orthogonal spreading codes and an echo delay is small enough that the echo of a chip is still within the same spreading interval time, and outputting filtered symbols.

32. The process of claim 31 wherein the states and coefficients of said digital equalizer and predictor filters are controlled to filter the symbols of one or more synchronous code division multiplexed (SCDMA) bursts in an synchronous code division multiplexed (SCDMA) frame during which one or more SCDMA bursts are transmitted simultaneously during one or more spreading intervals, said filtering process to filter the symbols of each burst carried out one SCDMA burst at a time and one spreading interval at a time, and wherein the states and coefficients of said digital equalizer and digital predictor filters are controlled by performing the following steps:

(1) at the beginning of each SCDMA frame, the states of said equalizer filter and said predictor filter are set to zero;

then, at the beginning of a first spreading interval in an SCDMA burst, the following steps are performed;

(2) loading predetermined predictor filter coefficients into said digital predictor filter, said predetermined predictor filter coefficients being adapted predictor filter coefficients stored in a predictor buffer at the end of the first spreading interval of the previous SCDMA burst in the same SCDMA frame;

then at the end of each spreading interval of an SCDMA burst, the following steps are performed;

(3) storing the state of said digital predictor filter in said predictor buffer either in a location dedicated to storing the state of said digital predictor filter for the spreading interval just processed or with tag data identifying the spreading interval number of the spreading interval just processed;

at the beginning of each spreading interval of an SCDMA burst, the following steps are performed;

(4) loading the state of said digital predictor filter with the state stored in said predictor buffer of said digital predictor filter at the end of the same number spreading interval of the previous SCDMA burst within the same SCDMA frame;

(5) loading the state of said digital equalization filter with all zeros;

at the beginning of only the first spreading interval of a burst, the following step is performed

(6) loading the filter coefficients of said digital equalization filter to default values, and thereafter adapting said filter coefficients during each spreading interval of said burst;

and wherein the step of filtering SCDMA bursts is accomplished by;

(7) filtering each symbol of each spreading interval of said SCDMA burst using a feed forward filter portion of said digital equalization filter;

(8) processing each symbol output by step (7) in a rotational amplifier using amplitude and phase offset correction factors calculated for the transmitter which transmitted said burst to calculate amplitude and phase offset corrected symbols;

(9) subtracting from each symbol output by step (8) the output of a digital feedback equalization filter;

(10) subtracting from each filtered symbol output from step (9) a corresponding output of said digital predictor filter to compute an output symbol;

(11) inputting each symbol output by step (10) into a slicer and comparing the input to said slicer to an output of said slicer to develop an error signal for each symbol;

(12) subtracting the output of said slicer from each symbol output by step (9) to calculate an interference estimate signal for each symbol;

(13) inputting each said error signal into a least mean squares (LMS) calculation process and using the results of said LMS process to adapt said filter coefficients of said digital predictor filter; and

(14) inputting each said interference estimate signal or said error signal into a least mean squares (LMS) process, and using the results of said LMS process to adapt the filter coefficients of said digital equalization filter.

33. The process of claim 32 further comprising the following steps:

(15) receiving symbols of null bursts transmitted on unused codes which bear no data and processing said symbols according to steps (1) through (14);

(16) examining the output of said slicer as each symbol which bears no data is processed thereby and calibrating said slicer to have an output of 0+j*0.

34. The process of claim 32 further comprising the following steps:

(17) loading said interference estimate signals into said predictor filter as its initial state as the symbols of said null burst are processed through said slicer; and

(18) using said error signal or said interference estimate signal generated as the symbols of said null burst are processed through said slicer as an input to an LMS algorithm and using the LMS algorithm to adapt the filter coefficients of the predictor filter to set its initial tap weights.

35. The process of claim 32 further comprising the following steps:

(15) receiving symbols of null bursts transmitted on unused codes which bear no data and processing said symbols according to steps (1) through (14);

(16) loading said interference estimate signals into the predictor filter as its initial state as the symbols of said null burst are processed through said slicer; and

(17) using said error signal or said interference estimate signal generated as the symbols of said null burst are processed through said slicer as an input to an LMS algorithm and using the LMS algorithm to adapt the filter coefficients of the predictor filter to set its initial tap weights.

36. The process of claim 32 further comprising the steps:

processing a preamble of known symbol data of at least some bursts in a preamble processor to develop initial amplitude and phase offset correction factors;

applying said initial amplitude and phase offset correction factors to first and second multipliers, respectively, of said rotational amplifier;

and wherein step (8) is accomplished by;

multiplying filtered symbols output by said feed forward digital equalization filter by said initial amplitude offset correction factor to output amplitude corrected symbols;

multiplying said amplitude corrected symbols by said phase offset correction factor to output amplitude and phase corrected symbols.

37. The process of claim 31 wherein the states and coefficients of said digital equalizer and predictor filters are controlled to filter the symbols of one or more synchronous code division multiplexed (SCDMA) bursts in an synchronous code division multiplexed (SCDMA) frame during which one or more SCDMA bursts are transmitted simultaneously during one or more spreading intervals, said filtering process to filter the symbols of each burst carried out one SCDMA burst at a time and one spreading interval at a time, and wherein the states and coefficients of said digital equalizer and digital predictor filters are controlled by performing the following steps:

(1) at the beginning of each SCDMA frame, the states of said equalizer filter and said predictor filter are set to zero;

then, at the beginning of a first spreading interval in an SCDMA burst, the following steps are performed;

(2) loading predetermined predictor filter coefficients into said digital predictor filter, said predetermined predictor filter coefficients being adapted predictor filter coefficients stored in a predictor buffer at the end of the first spreading interval of the previous SCDMA burst in the same SCDMA frame;

then at the end of each spreading interval of an SCDMA burst, the following steps are performed;

(3) storing the state of said digital predictor filter in said predictor buffer either in a location dedicated to storing the state of said digital predictor filter for the spreading interval just processed or with tag data identifying the spreading interval number of the spreading interval just processed;

at the beginning of each spreading interval of an SCDMA burst, the following steps are performed;

(4) loading the state of said digital predictor filter with the state stored in said predictor buffer of said digital predictor filter at the end of the same number spreading interval of the previous SCDMA burst within the same SCDMA frame;

(5) loading the state of said digital equalization filter with all zeros;

at the beginning of only the first spreading interval of a burst, the following step is performed

(6) loading the filter coefficients of said digital equalization filter to default values, and thereafter adapting said filter coefficients during each spreading interval of said burst;

and wherein the step of filtering each SCDMA burst is accomplished by;

(7) filtering each symbol of each spreading interval of said SCDMA burst using said digital feed forward equalization filter;

(8) subtracting from each filtered symbol output from step (7) an output of a digital feedback equalization filter to compute an equalized symbol;

(9) subtracting from each said equalized symbol the output of said predictor filter;

(10) processing each symbol output by step (9) with a rotational amplifier to correct amplitude and phase offset errors using amplitude and phase offsect correction factors developed for the transmitter which transmitted said burst;

(11) inputting each symbol output by step (10) into a slicer and comparing the input to said slicer to an output of said slicer to develop an error signal for each symbol;

(12) subtracting the output of said slicer from each symbol output by step (7) to calculate an interference estimate signal for each symbol;

(13) inputting each said error signal into a least mean squares (LMS) calculation process and using the results of said LMS process to adapt said filter coefficients of said digital predictor filter; and

(14) inputting each said interference estimate signal or said error signal into a least mean squares (LMS) process, and using the results of said LMS process to adapt the filter coefficients of said digital equalization filter.

38. The process of claim 37 further comprising the following steps:

(15) receiving symbols of null bursts transmitted on unused codes which bear no data and processing said symbols according to steps (1) through (14);

(16) examining the output of said slicer as each symbol which bears no data is processed thereby and calibrating said slicer to have an output of 0+j*0.

39. The process of claim 38 further comprising the following steps:

(17) loading said interference estimate signals into the predictor filter as its initial state as the symbols of said null burst are processed through said slicer; and

(18) using said error signal or said interference estimate signal generated as the symbols of said null burst are processed through said slicer as an input to said LMS algorithm and using the LMS algorithm to adapt the filter coefficients of the predictor filter to set its initial tap weights or filter coefficients.

40. The process of claim 37 further comprising the following steps:

(15) receiving symbols of null bursts transmitted on unused codes which bear no data and processing said symbols according to steps (1) through (14);

(16) loading said interference estimate signals into the predictor filter as its initial state as the symbols of said null burst are processed through said slicer; and

(17) using said error signal or said interference estimate signal generated as the symbols of said null burst are processed through said slicer as an input to an LMS algorithm and using the LMS algorithm to adapt the filter coefficients of the predictor filter to set its initial tap weights.

41. The process of claim 37 further comprising the steps:

(15) processing a preamble of known symbol data of at least some bursts in a preamble processor to develop initial amplitude and phase offset correction factors;

(16) applying said initial amplitude and phase offset correction factors to first and second multipliers, respectively, of said rotational amplifier;

and wherein step (10) is accomplished by

(17) multiplying filtered symbols output from step (9) by said initial amplitude offset correction factor to output amplitude corrected symbols;

(18) multiplying output by step (17) by said phase offset correction factor to output amplitude and phase corrected symbols for input to said slicer in step (11).

42. An error correction circuit for use in correcting symbol errors in received symbols of both time division multiplexed (TDMA) and synchronous code division multiplexed (SCDMA) bursts, comprising:

an input for receiving symbols of said TDMA bursts, and despread symbols of said SCDMA bursts;

a feed forward digital equalization filter (FFF) coupled to receive symbols at said input and having an output;

a rotational amplifier having an input coupled to said output of said FFF and having an output, and having a first input for receiving an amplitude offset correction factor and a second input for receiving a phase offset correction factor, both offset correction factors being unique to the transmitter which transmitted said burst;

a first summer having an output and having a first input coupled to said output of said rotational amplifier, and having a second input;

a second summer having an output, and having a first input coupled to said output of said first summer, and having a second input;

a symbol output coupled to said output of said second summer;

a slicer having an input coupled to said output of said second summer, and having an output;

a third summer having a first input coupled to said input of said slicer and a second input coupled coupled to said output of said slicer, and having an output at which an error signal appears;

a fourth summer having a first input coupled to said output of said first summer, and having a second input coupled to said output of said slicer, and having an output at which a interference estimate signal appears;

a first multiplier having an input coupled to receive said interference estimate signal, and having a multiplier input for receiving a $\frac{1}{\mathrm{\alpha <br><br>}}$

signal which is a complex number having the real part of the denominator α

equal to said amplitude offset correction factor input to said rotational amplifier and having the imaginary part of the denominator α

equal to said phase offset correction factor input to said rotational amplifier, and having an output at which the product of said interference estimate signal and said $\frac{1}{\mathrm{\alpha <br><br>}}$

signal appears;

a digital predictor filter having a state input coupled to said output of said first multiplier and having an output coupled to said second input of said second summer, and having one or more filter coefficient inputs;

a second multiplier having an input coupled to said output of said digital predictor filter and having an input at which a multiplier equal to α

is applied, and having an output at which the product of said state data times α

appears;

a predictor buffer coupled to store the states of said predictor filter at the end of each spreading interval of an SCDMA burst, and coupled to store the tap weight coefficients of said predictor filter at predetermined times;

a digital equalization feedback filter having a state input coupled to receive the output from said slicer, and having an output coupled to said second input of said first summer, and having filter coefficient inputs;

a computer or other control circuit controlling said error correction circuit according to a predetermined algorithm to remove errors caused by echoes and other noise from said TDMA and SCDMA bursts.

43. The apparatus of claim 42 wherein said computer or other control circuit is structured or programmed to control said error correction circuit to filter the symbols of one or more TDMA bursts, and, when a synchronous code division multiplexed (SCDMA) frame, during which one or more SCDMA bursts are transmitted simultaneously during one or more spreading intervals, is received, said computer or other control circuit is structured to filter the symbols of each said synchronous code division multiplexed (SCDMA) bursts one SCDMA burst at a time and one spreading interval at a time, and wherein said computer or other control circuit is structured to control the states and coefficients of said equalizer and predictor filters by performing the following steps to error correct SCDMA bursts:

(1) at the beginning of each SCDMA frame, the states of said equalizer filter and said predictor filter are set to zero;

then, at the beginning of a first spreading interval in an SCDMA burst, the following steps are performed;

(2) loading predetermined predictor filter coefficients into said predictor filter, said predetermined predictor filter coefficients being adapted predictor filter coefficients stored in said predictor buffer at the end of the first spreading interval of the previous SCDMA burst in the same SCDMA frame;

then at the end of each spreading interval of an SCDMA burst, the following steps are performed;

(3) storing the state of said predictor filter in said predictor buffer either in a location dedicated to storing the state of said predictor filter for the spreading interval just processed or with tag data identifying the spreading interval number of the spreading interval just processed;

at the beginning of each spreading interval of an SCDMA burst, the following steps are performed;

(4) loading the state of said predictor filter with the state stored in said predictor buffer of said predictor filter at the end of the same numbered spreading interval of the previous SCDMA burst within the same SCDMA frame;

(5) loading the state of said equalization filter with all zeros;

at the beginning of only the first spreading interval of a burst, the following step is performed

(6) loading the filter coefficients of said equalization filter to default values;

and for each SCDMA burst

(7) inputting each said error signal into a least mean squares (LMS) calculation process and using the results of said LMS process to adapt said filter coefficients of said predictor filter; and

(8) inputting each said interference estimate signal or said error signal into said least mean squares (LMS) process, and using the results of said LMS process to adapt the filter coefficients of said equalization filter.

44. The apparatus of claim 43 wherein said computer or other control circuitry is structured to control said error correction circuit to examine the output of said slicer when symbols of null bursts are received, and if the output of said slicer is not 0+j*0, applying a calibration signal to said slicer to calibrate its output to 0+j*0.

45. The apparatus of claim 43 wherein said computer or other control circuitry is structured to control said error correction circuit to load said inteference estimate signals into said predictor filter as its initial state as the symbols of null bursts are received and to feed said error or interference estimate signals to said LMS algorithm as the symbols of said null burst are being received and using the results of said LMS algorithm to set the initial tap weights of said predictor filter for processing SCDMA payload bursts.

46. The apparatus of claim 43 wherein said computer or other control circuitry is structured to control a preamble processor to process known preamble data of at least some bursts from each particular transmitter to generate and apply to control inputs of said rotational amplifier initial amplitude and phase offset correction factors peculiar to the transmitter which transmitted said burst;

and wherein said computer or other control circuitry is structured to control said error correction circuit to apply said error or interference estimate signals to said LMS algorithm and use the results of said LMS algorithm to adapt the values of said initial amplitude and phase offset correction factors during each spreading interval to develop fine tuned amplitude and phase offset correction factors for each burst from each transmitter.

47. An error correction circuit for use in correcting symbol errors in received symbols of both time division multiplexed (TDMA) and synchronous code division multiplexed (SCDMA) bursts, comprising:

an input for receiving symbols of said TDMA bursts, and despread symbols of said SCDMA bursts;

a feed forward digital equalization filter (FFF) coupled to receive symbols at said input and having an output;

a first summer having an output and having a first input coupled to said output of said FFF, and having a second input;

a second summer having an output, and having a first input coupled to said output of said first summer, and having a second input;

a rotational amplifier having an input coupled to said output of said second summer and having an output, and having a first input for receiving an amplitude offset correction factor and a second input for receiving a phase offset correction factor, both offset correction factors being unique to the transmitter which transmitted said burst;

a symbol output coupled to said output of said rotational amplifier;

a slicer having an input coupled to said output of said rotational amplifier, and having an output;

a third summer having a first input coupled to said input of said slicer and a second input coupled coupled to said output of said slicer, and having an output at which an error signal appears;

a fourth summer having a first input coupled to said output of said first summer, and having a second input coupled to said output of said slicer, and having an output at which a interference estimate signal appears;

a digital predictor filter having a state input coupled to said output of said fourth summer and having an output coupled to said second input of said second PATENT summer, and having one or more filter coefficient inputs;

a predictor buffer coupled to store the states of said predictor filter at the end of each spreading interval of an SCDMA burst, and coupled to store the tap weight coefficients of said predictor filter at predetermined times;

a digital equalization feedback filter having a state input coupled to receive the output from said slicer, and having an output coupled to said second input of said first summer, and having filter coefficient inputs;

a computer or other control circuit controlling said error correction circuit according to a predetermined algorithm to remove errors caused by echoes and other noise from said TDMA and SCDMA bursts.

48. The apparatus of claim 47 wherein said computer or other control circuit is structured or programmed to control said error correction circuit to filter the symbols of one or more TDMA bursts, and, when a synchronous code division multiplexed (SCDMA) frame, during which one or more SCDMA bursts are transmitted simultaneously during one or more spreading intervals, is received, said computer or other control circuit is structured to filter the symbols of each said synchronous code division multiplexed (SCDMA) bursts one SCDMA burst at a time and one spreading interval at a time, and wherein said computer or other control circuit is structured to control the states and coefficients of said equalizer and predictor filters by performing the following steps to error correct SCDMA bursts:

(1) at the beginning of each SCDMA frame, the states of said equalizer filter and said predictor filter are set to zero;

then, at the beginning of a first spreading interval in an SCDMA burst, the following steps are performed;

(2) loading predetermined predictor filter coefficients into said predictor filter, said predetermined predictor filter coefficients being adapted predictor filter coefficients stored in said predictor buffer at the end of the first spreading interval of the previous SCDMA burst in the same SCDMA frame;

then at the end of each spreading interval of an SCDMA burst, the following steps are performed;

(3) storing the state of said predictor filter in said predictor buffer either in a location dedicated to storing the state of said predictor filter for the spreading interval just processed or with tag data identifying the spreading interval number of the spreading interval just processed;

at the beginning of each spreading interval of an SCDMA burst, the following steps are performed;

(4) loading the state of said predictor filter with the state stored in said predictor buffer of said predictor filter at the end of the same numbered spreading interval of the previous SCDMA burst within the same SCDMA frame;

(5) loading the state of said equalization filter with all zeros;

at the beginning of only the first spreading interval of a burst, the following step is performed

(6) loading the filter coefficients of said equalization filter to default values;

and for each SCDMA burst

(7) inputting each said error signal into a least mean squares (LMS) calculation process and using the results of said LMS process to adapt said filter coefficients of said predictor filter; and

(8) inputting each said interference estimate signal or said error signal into said least mean squares (LMS) process, and using the results of said LMS process to adapt the filter coefficients of said equalization filter.

49. The apparatus of claim 47 wherein said computer or other control circuitry is structured to control said error correction circuit to examine the output of said slicer when symbols of null bursts are received, and if the output of said slicer is not 0+j*0, applying a calibration signal to said slicer to calibrate its output to 0+j*0.

50. The apparatus of claim 47 wherein said computer or other control circuitry is structured to control said error correction circuit to load said inteference estimate signals into said predictor filter as its initial state as the symbols of null bursts are received and to feed said error or interference estimate signals to said LMS algorithm as the symbols of said null burst are being received and using the results of said LMS algorithm to set the initial tap weights of said predictor filter for processing SCDMA payload bursts.

51. The apparatus of claim 47 wherein said computer or other control circuitry is structured to control a preamble processor to process known preamble data of at least some bursts from each particular transmitter to generate and apply to control inputs of said rotational amplifier initial amplitude and phase offset correction factors peculiar to the transmitter which transmitted said burst;

and wherein said computer or other control circuitry is structured to control said error correction circuit to apply said error or interference estimate signals to said LMS algorithm and use the results of said LMS algorithm to adapt the values of said initial amplitude and phase offset correction factors during each spreading interval to develop fine tuned amplitude and phase offset correction factors for each burst from each transmitter.