Sequential unique marking

• US 6,792,365 B2
• Filed: 08/10/2001
• Issued: 09/14/2004
• Est. Priority Date: 08/10/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Raitter, James S.
• Primary Examiner(s): CHARIOUI, MOHAMED
• Application Number:
  US09/928,032
• Publication Number:
  US 20030033101A1
• Time in Patent Office: 1,131 Days
• Field of Search: 702/35, 702/80-84, 702/117, 702/118, 702/187, 702/188, 700/121, 700/218, 209/573, 382/145, 438/14, 438/15, 438/17, 438/108
• US Class Current: 702/81
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2221/68313 Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling device, retrieving data from the tray map file, the data comprising unique characters correlating to each device of the plurality of devices and marking each device with the data

Claims

1. A method of unique sequential marking a plurality of semiconductor devices in a multi-die handling device comprising:

reading an ID code on said multi-die handling device;

retrieving a tray map file corresponding to said ID code;

determining a tray matrix of said multi-die handling device;

retrieving data from the tray map file, said data comprising unique characters correlating to each semiconductor device of said plurality of semiconductor devices; and

marking each semiconductor device with said data.

2. The method according to claim 1, wherein said data further comprises non-unique characters.

3. The method according to claim 2, wherein said non-unique characters are selected from the group consisting of semiconductor device data, date code, country code and company logo.

4. The method according to claim 1, wherein each semiconductor device comprises an integrated circuit semiconductor device.

5. The method according to claim 4, wherein said semiconductor device each comprise a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

6. The method according to claim 1, wherein said multi-die handling device comprises a JEDEC tray.

7. The method according to claim 1, wherein said unique characters comprise test data extracted for at least one semiconductor device from the tray map file.

8. The method of claim 1, wherein marking occurs before packaging each semiconductor device.

9. The method of claim 1, wherein marking occurs after packaging each semiconductor device.

10. A method of unique sequential marking comprising:

providing a multi-die handling device having a plurality of pockets therein in a matrix;

placing at least one semiconductor device in at least one pocket of said multi-die handling device;

reading an ID code on said multi-die handling device;

retrieving a tray map file corresponding to said ID code;

determining a tray matrix of said multi-die handling device;

retrieving data from the tray map file, said data comprising unique characters correlating to said at least one semiconductor device; and

marking said at least one semiconductor device with said data.

11. The method according to claim 10, wherein said data further comprises non-unique characters.

12. The method according to claim 11, wherein said non-unique characters comprise non-unique characters selected from the group consisting of semiconductor device data, date code, country code and company logo.

13. The method according to claim 10, wherein said at least one semiconductor device is an integrated circuit semiconductor device.

14. The method according to claim 13, wherein said semiconductor device each comprise a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

15. The method according to claim 10, wherein said multi-die handling device comprises a JEDEC tray.

16. The method according to claim 10, wherein said unique characters comprise test data extracted from said tray map file.

17. The method of claim 10, wherein marking occurs before packaging said at least one semiconductor device.

18. The method of claim 10, wherein marking occurs after packaging said at least one semiconductor device.

19. A method of culling semiconductor devices from a reject bin, said method comprising:

retrieving a plurality of semiconductor devices from at least one reject bin;

providing at least one carrier of a plurality of carriers having a plurality of pocket locations;

assigning said at least one carrier of said plurality of carriers an ID code;

placing each semiconductor device of said plurality of semiconductor devices in a pocket location of said plurality of pocket locations;

testing each semiconductor device;

generating a tray map file comprising test data corresponding to each semiconductor device;

storing the tray map file in association with the ID code of said at least one carrier;

reading the ID code on said at least one carrier;

retrieving the tray map file corresponding to said ID code;

determining a tray matrix of said at least one carrier;

retrieving test data from the tray map file; and

marking each semiconductor device of said plurality of semiconductor devices with the corresponding test data.

20. The method according to claim 19, wherein said carrier is a multi-die handling device.

21. The method according to claim 20, wherein said multi-die handling device comprises a JEDEC tray.

22. The method according to claim 19, wherein said test data comprises non-unique characters.

23. The method according to claim 22, wherein said non-unique characters comprise non-unique characters selected from the group consisting of semiconductor device data, date code, country code and company logo.

24. The method according to claim 19, wherein said semiconductor device each comprise a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs) and Dual In-Line Memory Modules (DIMMs).

25. The method of claim 19, wherein marking occurs before packaging each semiconductor device.

26. The method of claim 19, wherein marking occurs after packaging each semiconductor device.

27. A method of culling semiconductor devices from a reject bin, said method comprising:

retrieving a plurality of semiconductor devices from a reject bin;

providing a plurality of carriers, each carrier having a plurality of pocket locations in a tray matrix;

assigning each carrier of said plurality of carriers an ID code;

placing each semiconductor device of said plurality of semiconductor devices in a pocket location of said plurality of pocket locations;

testing each semiconductor device;

generating a tray map file comprising test data corresponding to each semiconductor device;

storing the tray map file in association with the ID code of each carrier;

reading the ID code on a carrier;

retrieving the tray map file corresponding to said ID code;

determining a tray matrix of the carrier;

retrieving test data from the tray map file; and

marking each semiconductor device of said plurality of semiconductor devices with the corresponding test data.

28. The method according to claim 27, wherein said carrier comprises a multi-die handling device.

29. The method according to claim 28, wherein said multi-die handling device comprises a JEDEC tray.

30. The method according to claim 27, wherein said test data comprises non-unique characters.

31. The method according to claim 30, wherein said non-unique characters comprise non-unique characters selected from the group consisting of semiconductor device data, date code, country code and company logo.

32. The method according to claim 27, wherein said semiconductor device each comprise a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

33. The method of claim 27, wherein marking occurs before packaging each semiconductor device.

34. The method of claim 27, wherein marking occurs after packaging each semiconductor device.