Methods and apparatus for semiconductor testing

• US 6,792,373 B2
• Filed: 05/24/2002
• Issued: 09/14/2004
• Est. Priority Date: 05/24/2001
• Status: Expired due to Term

• Current Assignee: In-Depth Test LLC (Acacia Research Corporation)
• Original Assignee: Test Advantage Incorporated (Boston Semi Equipment, LLC)
• Inventors: Tabor, Eric Paul
• Primary Examiner(s): Bui, Bryan
• Application Number:
  US10/154,627
• Publication Number:
  US 20030014205A1
• Time in Patent Office: 844 Days
• Field of Search: 702/84, 702/108, 702/117, 702/118, 702/119, 702/120, 702/121, 702/122, 702/123, 702/124, 702/125, 702/179, 702/182, 702/183, 702/187, 702/189, 702/190, 714/721, 714/724, 438/10, 438/14
• US Class Current: 702/108
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and apparatus for testing semiconductors according to various aspects of the present invention comprises a test system comprising an outlier identification element configured to identify significant data in a set of test results. The test system may be configured to provide the data in an output report. The outlier identification element suitably performs the analysis at run time. The outlier identification element may also operate in conjunction with a smoothing system to smooth the data and identify trends and departures from test result norms.

Claims

1. A test system, comprising:

a tester configured to test a component and generate test data; and

a computer connected to the tester and configured to receive the test data, identify an outlier in the test data, and generate an output report including the identified outlier.

2. A test system according to claim 1, wherein the computer is configured to operate in conjunction with a set of configuration data in a recipe file.

3. A test system according to claim 1, wherein the test data corresponds to a section group of components on a wafer.

4. A test system according to claim 1, wherein the computer is configured to automatically calibrate a sensitivity of the computer to the test data.

5. A test system according to claim 1, wherein the computer further comprises a data correlation element configured to correlate the test data.

6. A test system according to claim 1, wherein the computer is configured to identify the outlier at run time.

7. A test system according to claim 1, wherein the computer further comprises a data smoothing element configured to receive the test data and smooth the test data, and wherein the computer is configured to receive the smoothed test data and identify the outlier in the smoothed test data.

8. A data analysis system for semiconductor test data, comprising a computer system, wherein the computer system is configured to operate:

a supplementary data analysis element configured to identify outliers in the semiconductor test data; and

an output element configured to generate an output report including the identified outliers.

9. A data analysis system according to claim 8, wherein the supplementary data analysis element is configured to operate in conjunction with a set of configuration data in a recipe file.

10. A data analysis system according to claim 8, wherein the test data corresponds to a section group of components on a wafer.

11. A data analysis system according to claim 8, wherein the supplementary data analysis element is configured to automatically calibrate a sensitivity of the outlier identification element to the test data.

12. A data analysis system according to claim 8, wherein the supplementary data analysis element includes a data correlation element configured to correlate the test data.

13. A data analysis system according to claim 8, wherein the supplementary data analysis element is configured to identify the outliers at run time.

14. A data analysis system according to claim 8, wherein the supplementary data analysis element includes a data smoothing element configured to receive the test data and smooth the test data, and wherein the supplementary data analysis element is configured to identify the outliers in the smoothed test data.

15. A method for testing semiconductors, comprising:

generating test data for multiple components; and

automatically identifying an outlier in the test data at run time using a computer system.

16. A method according to claim 15, further comprising reading configuration data from a recipe file using the computer system, wherein identifying the outlier includes identifying the outlier according to the configuration data in the recipe file.

17. A method according to claim 15, wherein the test data corresponds to a section group of components on a wafer.

18. A method according to claim 15, further comprising calibrating a sensitivity for identifying the outlier in the test data using the computer system.

19. A method according to claim 15, further comprising smoothing the test data using the computer system.

20. A method according to claim 15, further comprising correlating the test data to identify similarities in the test data using the computer system.