Method for testing I/O ports of a computer motherboard

• US 6,792,378 B2
• Filed: 11/21/2002
• Issued: 09/14/2004
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chen, Chao-An, Huang, Chih-Wei, Chen, Zhiguo
• Primary Examiner(s): Shah, Kamini
• Application Number:
  US10/300,762
• Publication Number:
  US 20040102916A1
• Time in Patent Office: 663 Days
• Field of Search: 702/80, 702/117, 702/11, 702/8, 702/119, 700/20, 700/21, 714/6, 714/7, 714/8, 714/15, 714/25
• US Class Current: 702/119
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]

Abstract

A method for testing I/O ports of a computer motherboard under test. A non-volatile memory on the computer motherboard under test is provided with a test code for initializing the computer motherboard and testing its I/O ports, in which the test code includes a plurality of test routines corresponding to the I/O ports to be tested. Upon power-up or reboot, the computer motherboard under test is booted from the test code in the non-volatile memory. One of the I/O ports is selected from an interactive display menu, and then a CPU on the computer motherboard under test executes the corresponding test routine for the selected I/O port to test it. If there is an abnormal signal pin in the selected I/O port, a failure message is displayed to indicate which signal pin of the selected I/O port is not operating correctly. Otherwise, a pass message is displayed.

Claims

1. A method for testing I/O ports of a computer motherboard, comprising the steps of:

providing a non-volatile memory on the computer motherboard with a test code for initializing the computer motherboard and testing the I/O ports thereof, in which the test code includes a plurality of test routines corresponding to the I/O ports;

booting the computer motherboard from the test code in the non-volatile memory;

selecting one of the I/O ports to be tested from a display menu;

executing the corresponding test routine for the selected I/O port to test the selected I/O port on the basis of the selected I/O port'"'"'s characteristics;

displaying a pass message if every signal pin of the selected I/O port is operating correctly; and

displaying a failure message to indicate which signal pin of the selected I/O port is not operating correctly if there is an abnormal signal pin in the selected I/O port.

2. The method as recited in claim 1 wherein the selected I/O port under test is a game port of the computer motherboard.

3. The method as recited in claim 2 wherein the step of executing the corresponding test routine further comprises:

detecting corresponding diagnostic values from respective game interface pins of the game port;

comparing predetermined values set externally for the respective game interface pins of the game port with the detected diagnostic values; and

if the detected diagnostic values and the predetermined values are well-matched, determining that all of the game interface pins are operating correctly.

4. The method as recited in claim 3 wherein the game port supports two joystick connections each of which has the game interface pins including a first button input pin, a second button input pin, an X-axis position input pin and a Y-axis position input pin.

5. The method as recited in claim 1 wherein the selected I/O port under test is a parallel port of the computer motherboard.

6. The method as recited in claim 5 wherein the step of executing the corresponding test routine further comprises:

(a) sending a first bit pattern out of a first portion of parallel interface data pins of the parallel port;

(b) receiving a first result from a first parallel interface status pin of the parallel port after a predetermined time to check the first parallel interface status pin based on the relationship between the received first result and the sent first bit pattern;

(c) sending a set of second bit patterns one at a time out of the first portion of the parallel interface data pins of the parallel port;

(d) after the predetermined time, receiving one second result at a time from the first parallel interface status pin of the parallel port;

(e) repeating the steps (c) through (d) to check every parallel interface data pin in the first portion of the parallel interface data pins based on the relationship between the second result received each time in the step (d) and the corresponding second bit pattern;

(f) sending the first bit pattern out of a second portion of parallel interface data pins of the parallel port;

(g) receiving a third result from a second parallel interface status pin of the parallel port after the predetermined time to check the second parallel interface status pin based on the relationship between the received third result and the sent first bit pattern;

(h) sending the set of second bit patterns one at a time out of the second portion of the parallel interface data pins of the parallel port;

(i) after the predetermined time, receiving one fourth result at a time from the second parallel interface status pin of the parallel port;

(j) repeating the steps (h) through (i) to check every parallel interface data pin in the second portion of the parallel interface data pins based on the relationship between the fourth result received each time in the step (i) and the corresponding second bit pattern;

(k) sending the first bit pattern out of a set of parallel interface control pins of the parallel port;

(l) receiving a fifth result from a third parallel interface status pin of the parallel port after the predetermined time to check the third parallel interface status pin based on the relationship between the received fifth result and the sent first bit pattern;

(m) sending the set of second bit patterns one at a time out of the set of the parallel interface control pins of the parallel port;

(n) after the predetermined time, receiving one sixth result at a time from the third parallel interface status pin of the parallel port;

(o) repeating the steps (m) through (n) to check every parallel interface control pin in the set of the parallel interface control pins based on the relationship between the sixth result received each time in the step (n) and the corresponding second bit pattern;

(p) detecting a seventh and eighth result from a fourth and fifth parallel interface status pin of the parallel port;

(q) comparing predetermined values set externally for the fourth and the fifth parallel interface status pins with the detected seventh and the eighth results; and

(r) if the seventh and the eighth results match the predetermined values, determining that the fourth and the fifth parallel interface status pins of the parallel port are operating correctly.

7. The method as recited in claim 6 wherein the first parallel interface status pin is a P/E status pin, the second parallel interface status pin is a SELECT status pin, the third parallel interface status pin is an ERROR status pin, the fourth parallel interface status pin is an ACK status pin, and the fifth parallel interface status pin is a BUSY status pin.

8. The method as recited in claim 6 wherein the first portion and the second portion of the parallel interface data pins constitute eight DATA pins of the parallel port.

9. The method as recited in claim 6 wherein the set of the parallel interface control pins includes a SLIN control pin, an INIT control pin, an A/F control pin, and a STROBE control pin.

10. The method as recited in claim 1 wherein the selected I/O port under test is a serial port of the computer motherboard.

11. The method as recited in claim 10 wherein the step of executing the corresponding test routine further comprises:

configuring the serial port at a predetermined baud rate;

sending predetermined data out of a first serial interface control pin of the serial port;

receiving a first and second result from a first and second serial interface status pin of the serial port after a predetermined time;

respectively checking whether the first and the second results are equal to the predetermined data, verifying the first and the second serial interface status pins and the first serial interface control pin;

sending the predetermined data out of a second serial interface control pin of the serial port;

receiving a third and fourth result from a third and fourth serial interface status pin of the serial port after the predetermined time;

respectively checking whether the third and the fourth results are equal to the predetermined data, verifying the third and the fourth serial interface status pins and the second serial interface control pin;

disabling a receiver function related to the serial port under test;

transmitting a bit pattern out of a serial data output pin of the serial port;

enabling the receiver function related to the serial port under test after the predetermined time;

receiving incoming data bits from a serial data input pin of the serial port; and

checking whether the incoming data bits and the bit pattern are well-matched verifying the serial data input pin and the serial data output pin.

12. The method as recited in claim 11 wherein the first serial interface control pin is a DTR pin of the serial port and the second serial interface control pin is a RTS pin of the serial port.

13. The method as recited in claim 11 wherein the first serial interface status pin is a DCD pin of the serial port, the second serial interface status pin is a DSR pin of the serial port, the third serial interface status pin is a CTS pin of the serial port, and the fourth serial interface status pin is a RI pin of the serial port.

14. The method as recited in claim 11 wherein the serial data output pin is a TXD pin of the serial port and the serial data input pin is a RXD pin of the serial port.

15. The method as recited in claim 14 further comprising the steps of:

if the TXD and the RXD pins are operating correctly, performing the following steps;

(a) configuring the serial port at a new baud rate;

(b) disabling the receiver function related to the serial port under test;

(c) transmitting the bit pattern out of the TXD pin of the serial port;

(d) enabling the receiver function related to the serial port under test after the predetermined time;

(e) receiving new incoming data bits from the RXD pin of the serial port;

(f) checking whether the new incoming data bits and the bit pattern are well-matched, verifying the serial port under test for the new baud rate; and

(g) repeating the steps (a) through (f) until all of the configurable baud rates for the serial port are tested.

16. The method as recited in claim 1 wherein the selected I/O port under test is a universal serial bus (USB) port of the computer motherboard.

17. The method as recited in claim 16 wherein the step of executing the corresponding test routine further comprises:

detecting a diagnostic value from a pair of differential data pins of the USB port;

comparing a default value for the USB port with the detected diagnostic value; and

if the detected diagnostic value is different from the default value for the USB port, determining that the pair of differential data pins of the USB port are operating correctly.

18. The method as recited in claim 1 wherein the selected I/O port under test is a network port of the computer motherboard.

19. The method as recited in claim 18 wherein the step of executing the corresponding test routine further comprises:

loopback-connecting a pair of transmit pins of the network port to a pair of receive pins of the network port;

identifying an I/O base address for the network port;

reading a memory block allocated from the network port I/O base address;

checking the transmit pins and the receive pins with corresponding bits in the memory block where the corresponding bits directly reflect the current status of the pair of transmit pins and the pair of receive pins; and

if diagnostic values represented by the corresponding bits in the memory block are different from the network port'"'"'s default values, determining that the pair of transmit pins and the pair of receive pins are operating correctly.

20. The method as recited in claim 1 wherein the selected I/O port under test is an audio port of the computer motherboard.

21. The method as recited in claim 20 wherein the step of executing the corresponding test routine further comprises:

receiving a test signal from a first audio input pin of the audio port;

checking whether the received test signal continues changing;

determining that the first audio input pin is operating correctly if the received test signal continues changing;

sending predetermined test data out of a first output pin of the audio port;

receiving first incoming data from a second audio input pin of the audio port;

comparing the predetermined test data with the first incoming data;

if the predetermined test data matches the first incoming data, determining that the first output and the second audio input pins are operating correctly; and

sending the predetermined test data out of a second output pin of the audio port;

receiving second incoming data from a third audio input pin of the audio port;

comparing the predetermined test data with the second incoming data; and

if the predetermined test data matches the second incoming data, determining that the second output and the third audio input pins are operating correctly.

22. The method as recited in claim 21 wherein the first input output pin is a microphone pin of the audio port, the first and the second output pins form a pair of stereo output pins of the audio port, and the second and the third audio input pins form a pair of stereo input pins of the audio port.

23. The method as recited in claim 1 wherein the selected I/O port under test is a keyboard port of the computer motherboard.

24. The method as recited in claim 23 wherein the step of executing the corresponding test routine further comprises:

sending predetermined test data out of a clock pin of the keyboard port;

receiving incoming data from a data pin of the keyboard port;

comparing the predetermined test data with the incoming data; and

if the predetermined test data matches the incoming data, determining that the clock and the data pins of the keyboard port are operating correctly.

25. The method as recited in claim 1 wherein the selected I/O port under test is a PS/2 mouse port of the computer motherboard.

26. The method as recited in claim 25 wherein the step of executing the corresponding test routine further comprises:

sending predetermined test data out of a clock pin of the PS/2 mouse port;

receiving incoming data from a data pin of the PS/2 mouse port;

comparing the predetermined test data with the incoming data; and

if the predetermined test data matches the incoming data, determining that the clock and the data pins of the PS/2 mouse port are operating correctly.

27. A method for testing I/O ports of a computer motherboard having a central processing unit (CPU) and a non-volatile memory storing a basic input-output system (BIOS) code, the method comprising the steps of:

providing the non-volatile memory with a test code instead of the BIOS code for initializing the computer motherboard and testing the I/O ports thereof, in which the test code includes a plurality of test routines corresponding to the I/O ports;

booting the CPU from the test code in the non-volatile memory whereby the CPU executes the test code to test the I/O ports of the computer motherboard;

interactively selecting one of the I/O ports to be tested from a display menu;

executing the corresponding test routine for the selected I/O port to test the selected I/O port on the basis of the selected I/O port'"'"'s characteristics;

displaying a pass message if every signal pin of the selected I/O port is operating correctly; and

displaying a failure message to indicate which signal pin of the selected I/O port is not operating correctly if there is an abnormal signal pin in the selected I/O port.

28. The method as recited in claim 27 wherein the selected I/O port under test is a game port of the computer motherboard.

29. The method as recited in claim 28 wherein the step of executing the corresponding test routine further comprises:

initializing an I/O base address for the game port;

reading a memory block allocated from the game port I/O base address;

checking every game interface pin of the game port with corresponding bits in the memory block where the bits directly reflect the current status of the game interface pins under check;

comparing predetermined values set externally for the respective game interface pins of the game port with the corresponding bits in the memory block; and

if the corresponding bits in the memory block and the predetermined values are well-matched, determining that all the game interface pins are operating correctly.

30. The method as recited in claim 29 wherein the game port supports two joystick connections each of which has the game interface pins including a first button input pin, a second button input pin, an X-axis position input pin and a Y-axis position input pin.

31. The method as recited in claim 27 wherein the selected I/O port under test is a parallel port of the computer motherboard.

32. The method as recited in claim 31 wherein the step of executing the corresponding test routine further comprises:

(a) initializing an I/O base address for the parallel port;

(b) writing a first bit pattern to a first portion of data bits in a memory block corresponding to a first portion of parallel interface data pins of the parallel port, in which the memory block is allocated from the parallel port I/O base address;

(c) reading a first status bit in the memory block corresponding to a first parallel interface status pin of the parallel port after a predetermined time to check the first parallel interface status pin based on the relationship between the first status bit read from the memory block and the first bit pattern;

(d) writing a set of second bit patterns one at a time to the first portion of the data bits in the memory block corresponding to the first portion of the parallel interface data pins of the parallel port;

(e) reading the first status bit in the memory block corresponding to the first parallel interface status pin of the parallel port after the predetermined time;

(f) repeating the steps (d) through (e) to check every parallel interface data pin in the first portion of the parallel interface data pins based on the relationship between the first status bit read each time in the step (e) and the corresponding second bit pattern;

(g) writing the first bit pattern to a second portion of the data bits in the memory block corresponding to a second portion of the parallel interface data pins of the parallel port;

(h) reading a second status bit in the memory block corresponding to a second parallel interface status pin of the parallel port after the predetermined time to check the second parallel interface status pin based on the relationship between the second status bit read from the memory block and the first bit pattern;

(i) writing the set of second bit patterns one at a time to the second portion of the data bits in the memory block corresponding to the second portion of the parallel interface data pins of the parallel port;

(j) reading the second status bit in the memory block corresponding to the second parallel interface status pin of the parallel port after the predetermined time;

(k) repeating the steps (i) through (j) to check every parallel interface data pin in the second portion of the parallel interface data pins based on the relationship between the second status bit read each time in the step (j) and the corresponding second bit pattern;

(l) writing the first bit pattern to a set of control bits in the memory block corresponding to a set of parallel interface control pins of the parallel port;

(m) reading a third status bit in the memory block corresponding to a third parallel interface status pin of the parallel port after the predetermined time to check the third parallel interface status pin based on the relationship between the third status bit read from the memory block and the first bit pattern;

(n) writing the set of second bit patterns one at a time to the set of the control bits in the memory block corresponding to the set of the parallel interface control pins of the parallel port;

(o) reading the third status bit in the memory block corresponding to the third parallel interface status pin of the parallel port after the predetermined time;

(p) repeating the steps (n) through (o) to check every parallel interface control pin in the set of the parallel interface control pins based on the relationship between the third status bit read each time in the step (o) and the corresponding second bit pattern;

(q) directly reading a fourth and fifth status bit in the memory block corresponding to a fourth and fifth parallel interface status pin of the parallel port;

(r) comparing predetermined values set externally for the fourth and the fifth parallel interface status pins with the fourth and the fifth status bits in the memory block; and

(s) if the fourth and the fifth status bits in the memory block and the predetermined values are well-matched, determining that the fourth and the fifth parallel interface status pins of the parallel port are operating correctly.

33. The method as recited in claim 32 wherein the first parallel interface status pin is a P/E status pin, the second parallel interface status pin is a SELECT status pin, the third parallel interface status pin is an ERROR status pin, the fourth parallel interface status pin is an ACK status pin, and the fifth parallel interface status pin is a BUSY status pin.

34. The method as recited in claim 32 wherein the first portion and the second portion of the parallel interface data pins constitute eight DATA pins of the parallel port.

35. The method as recited in claim 32 wherein the set of the parallel interface control pins includes a SLIN control pin, an INIT control pin, an A/F control pin, and a STROBE control pin.

36. The method as recited in claim 27 wherein the selected I/O port under test is a serial port of the computer motherboard.

37. The method as recited in claim 36 wherein the step of executing the corresponding test routine further comprises:

initializing an I/O base address for the serial port;

configuring the serial port at a predetermined baud rate;

writing a predetermined data bit to a first serial interface control bit in a memory block corresponding to a first serial interface control pin of the serial port, in which the memory block is allocated from the serial port I/O base address;

reading a first and second serial interface status bit in the memory block corresponding to a first and second serial interface status pin of the serial port after a predetermined time;

respectively checking whether the first and the second serial interface status bits are equal to the predetermined data bit written to the first serial interface control bit, verifying the first and the second serial interface status pins and the first serial interface control pin;

writing the predetermined data bit to a second serial interface control bit in the memory block corresponding to a second serial interface control pin of the serial port;

reading a third and fourth serial interface status bit in the memory block corresponding to a third and fourth serial interface status pin of the serial port after the predetermined time;

respectively checking whether the third and the fourth serial interface status bits are equal to the predetermined data bit written to the second serial interface control bit, verifying the third and the fourth serial interface status pins and the second serial interface control pin;

disabling a receiver function related to the serial port under test;

writing a bit pattern to transmitter data bits in the memory block for a serial data output pin of the serial port;

enabling the receiver function related to the serial port under test after the predetermined time;

reading receiver data bits in the memory block for a serial data input pin of the serial port; and

checking whether the receiver data bits in the memory block and the bit pattern are well-matched verifying the serial data input pin and the serial data output pin.

38. The method as recited in claim 37 wherein the first serial interface control pin is a DTR pin of the serial port and the second serial interface control pin is a RTS pin of the serial port.

39. The method as recited in claim 37 wherein the first serial interface status pin is a DCD pin of the serial port, the second serial interface status pin is a DSR pin of the serial port, the third serial interface status pin is a CTS pin of the serial port, and the fourth serial interface status pin is a RI pin of the serial port.

40. The method as recited in claim 37 wherein the serial data output pin is a TXD pin of the serial port and the serial data input pin is a RXD pin of the serial port.

41. The method as recited in claim 40 further comprising the steps of:

if the TXD and the RXD pins are operating correctly, then performing the following steps;

(a) configuring the serial port at a new baud rate;

(b) disabling the receiver function related to the serial port under test;

(c) writing the bit pattern to the transmitter data bits in the memory block for the TXD pin of the serial port;

(d) enabling the receiver function related to the serial port under test after the predetermined time;

(e) reading the receiver data bits in the memory block for the RXD pin of the serial port;

(f) checking whether the receiver data bits in the memory block and the bit pattern are well-matched verifying the serial port under test for the new baud rate; and

(g) repeating the steps (a) through (f) until all of the configurable baud rates for the serial port are tested.

42. The method as recited in claim 27 wherein the selected I/O port under test is a universal serial bus (USB) port of the computer motherboard.

43. The method as recited in claim 42 wherein the step of executing the corresponding test routine further comprises:

identifying an I/O base address for the USB port;

reading a memory block allocated from the USB port I/O base address;

checking a pair of differential data pins of the USB port with corresponding bits in the memory block where the corresponding bits directly reflect the current status of the pair of differential data pins; and

if a diagnostic value represented by the corresponding bits in the memory block is different from the USB port'"'"'s default value, determining that the pair of differential data pins of the USB port are operating correctly.

44. The method as recited in claim 27 wherein the selected I/O port under test is a network port of the computer motherboard.

45. The method as recited in claim 44 wherein the step of executing the corresponding test routine further comprises:

loopback-connecting a pair of transmit pins of the network port to a pair of receive pins of the network port;

scanning a peripheral bus to find a network controller for the network port of the computer motherboard;

reading a vendor identification and a device identification of the network controller;

determining if the type of the network controller can be supported in accordance with the vendor identification and the device identification;

identifying an I/O base address for the network port;

checking whether a MAC address for the network controller is legal;

reading a memory block allocated from the network port I/O base address;

checking the transmit pins and the receive pins with corresponding bits in the memory block where the corresponding bits directly reflect the current status of the pair of transmit pins and the pair of receive pins; and

if diagnostic values represented by the corresponding bits in the memory block are different from the network port'"'"'s default values, determining that the pair of transmit pins and the pair of receive pins are operating correctly.

46. The method as recited in claim 27 wherein the selected I/O port under test is an audio port of the computer motherboard.

47. The method as recited in claim 46 wherein the step of executing the corresponding test routine further comprises:

receiving a test signal from a first audio input pin of the audio port;

checking whether the received test signal continues changing;

determining that the first audio input pin is operating correctly if the received test signal continues changing;

sending predetermined test data out of a first output pin of the audio port;

receiving first incoming data from a second audio input pin of the audio port;

comparing the predetermined test data with the first incoming data;

if the predetermined test data matches the first incoming data, determining that the first output and the second audio input pins are operating correctly; and

sending the predetermined test data out of a second output pin of the audio port;

receiving second incoming data from a third audio input pin of the audio port;

comparing the predetermined test data with the second incoming data; and

if the predetermined test data matches the second incoming data, determining that the second output and the third audio input pins are operating correctly.

48. The method as recited in claim 47 wherein the first input output pin is a microphone pin of the audio port, the first and the second output pins form a pair of stereo output pins of the audio port, and the second and the third audio input pins form a pair of stereo input pins of the audio port.