Method for fabricating a memory cell

• US 6,794,249 B2
• Filed: 02/28/2003
• Issued: 09/21/2004
• Est. Priority Date: 06/21/2001
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Willer, Josef, Palm, Herbert
• Primary Examiner(s): Nguyen, Cuong
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US10/378,101
• Publication Number:
  US 20030151091A1
• Time in Patent Office: 571 Days
• Field of Search: 257/330, 257/331, 257/332, 257/333, 257/334, 438/259, 438/270, 438/191, 438/589
• US Class Current: 438/259
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.

Claims

1. A method for fabricating a memory cell, which comprises:

in a first step, patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer;

forming a doped region for a source and a doped region for a drain using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the first step;

in a second step, forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench;

in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material; and

in a fourth step, introducing an electrically conductive material for a gate electrode into the trench and patterning the electrically conductive material to form at least one conductor track that is provided as a word line.

2. The method according to claim 1, which comprises, in the first step, providing a layer sequence including a polysilicon layer and a metal-containing layer as the electrically conductive layer.

3. The method according to claim 2, which comprises, providing the metal-containing layer with at least one film layer of a material selected from the group consisting of WSi, WN, and W.

4. The method according to claim 1, which comprises:

in the step of forming the doped region for the source and the doped region for the drain includes, forming a plurality of doped regions serving as source regions and drain regions;

in the second step, forming a plurality of trenches running parallel to each other and having sides between the strip-like sections of the electrically conductive layer such that one of the plurality of the doped regions serving as a source region remains at one of the sides of each one of the plurality of the trenches and such that another one of the plurality of the doped regions serving as a drain region remains at another one of the sides of each one of the plurality of the trenches; and

in the fourth step, introducing the electrically conductive material into the plurality of the trenches to form a plurality of gate electrodes.

5. A method for fabricating a memory cell, which comprises:

in a first step, fabricating at least one film of a patterning layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer;

in a second step, forming a trench having sides between the strip-like sections of the patterning layer so that regions of the semiconductor material serving as a source region and as a drain region remain at the sides of the trench;

in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material;

in a fourth step, introducing an electrically conductive material for a gate electrode into the trench;

in a fifth step, replacing the strip-like sections of the patterning layer with strip-like sections of an electrically conductive layer;

in a sixth step, applying at least one conductor track serving as a word line such that that the conductor track electrically contacts the electrically conductive material that has been introduced into the trench and such that the conductor track is electrically isolated from the strip-like sections of the electrically conductive layer; and

forming doped regions that serve as the source region and the drain region using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the fifth step.

6. The method according to claim 5, which comprises:

using silicon as the semiconductor material that is selected from the group consisting of the semiconductor body and the semiconductor layer; and

in the fifth step, using at least one film of a silicided metal as the electrically conductive layer.

7. The method according to claim 6, which comprises forming a film of cobalt silicide in the fifth step.

8. The method according to claim 5, which comprises:

in the second step, forming a plurality of trenches running parallel to each other and having sides between the strip-like sections of the electrically conductive layer such that a respective region of the semiconductor material serving as a source region remains at one of the sides of each one of the plurality of the trenches and such that another respective region of the semiconductor material serving as a drain region remains at another one of the sides of each one of the plurality of the trenches;

in the fourth step, introducing the electrically conductive material into the plurality of the trenches to form a plurality of gate electrodes; and

in the step of forming the doped regions that serve as the source region and the drain region, forming a plurality of doped regions serving as source regions and drain regions.