Method of making a power semiconductor device

• US 6,794,251 B2
• Filed: 04/16/2003
• Issued: 09/21/2004
• Est. Priority Date: 12/31/2001
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/414,949
• Publication Number:
  US 20030203552A1
• Time in Patent Office: 524 Days
• Field of Search: 438/268-270, 438/560-563
• US Class Current: 438/268
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A power semiconductor device made in accordance with a method comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. depositing in said trench a second layer of material having a first dopant of the first conductivity type;

6. interdiffusing the first and second dopants respectively located in the second and first layers of material to achieve electrical compensation in the first and second layers of material;

D. forming over said voltage sustaining region at least one region of said second conductivity type to define junction therebetween.

2. A power semiconductor device made in accordance with a method comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. depositing in said trench a second layer of material having a first dopant of the first conductivity type;

6. interdiffusing the first and second dopants respectively located in the second and first layers of material to achieve electrical compensation in the first and second layers of material;

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,

wherein step (C) further includes the steps of;

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively, and

wherein said first and second layers of material are layers of polysilicon.

3. A power semiconductor device made in accordance with a method comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. depositing in said trench a second layer of material having a first dopant of the first conductivity type;

6. interdiffusing the first and second dopants respectively located in the second and first layers of material to achieve electrical compensation in the first and second layers of material;

D. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween, and

wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a diode and a bipolar transistor.