Mask ROM structure and method of fabricating the same

• US 6,794,253 B2
• Filed: 02/24/2003
• Issued: 09/21/2004
• Est. Priority Date: 02/24/2003
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lee, Hsiang-Pang, Lin, Shang-Ping, Chou, Tsung-Yi, Yang, Chun-Yi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/248,832
• Publication Number:
  US 20040166639A1
• Time in Patent Office: 575 Days
• Field of Search: 438/276, 438/275, 438/277
• US Class Current: 438/276
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM

Abstract

A method of fabricating a mask ROM is provided, gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.

Claims

1. A method of fabricating a mask read-only-memory, comprising the steps of:

providing a substrate;

sequentially forming gate dielectric and a plurality of first conductive strips over the substrate;

forming a first dielectric layer over the first conductive strips;

patterning the first dielectric layer to form a plurality of first coding openings, wherein each first coding opening exposes the first conductive strip;

forming a first well in the first conductive strip at the bottom of each first coding opening; and

forming a plurality of second conductive strips over the first dielectric layer and inside the first coding openings, wherein the second conductive strips connect electrically with their respective first wells to from a first memory cell array.

2. The method of claim 1, wherein material constituting the first conductive strips includes doped polysilicon.

3. The method of claim 1, wherein the first conductive strips have a doping state (N+ type) that differs from the doping state of the first wells (P+ type).

4. The method of claim 1, wherein material constituting the second conductive strips is selected from a group consisting of aluminum, tungsten, copper and doped polysilicon.

5. The method of claim 1, wherein the first conductive strips are aligned in a direction perpendicular to the second conductive strips.

6. The method of claim 1, wherein step of forming the mask ROM may further include forming a word line between each gate oxide layer and each first conductive strip.

7. The method of claim 1, wherein after the step of forming the second conductive strips over the first dielectric layer and inside the first coding openings, may further include the steps of:

(a) forming a second dielectric layer over the first dielectric layer and the second conductive strips;

(b) forming a plurality of third conductive strips over the second dielectric layer;

(c) forming a third dielectric layer over the second dielectric layer and the third conductive strips;

(d) patterning the third dielectric layer to form a plurality of second coding openings, wherein each second coding opening exposes the third conductive strip;

(e) forming a second well in the third conductive strip at the bottom of each second coding opening; and

(f) forming a plurality of fourth conductive strips over the third dielectric layer and inside the coding openings, wherein the fourth conductive strips connect electrically with the respective second wells to form a second memory cell array.

8. The method of claim 7, wherein material constituting the third conductive strips includes doped polysilicon.

9. The method of claim 7, wherein the third conductive strips have a doping state that differs from the doping state of the second wells.

10. The method of claim 7, wherein material constituting the fourth conductive strips is selected from a group consisting of aluminum, tungsten, copper and doped polysilicon.

11. The method of claim 7, wherein the third conductive strips are aligned in a direction perpendicular to the fourth conductive strips.

12. The method of claim 7, after performing the steps from (a) to (f), further includes repeating the steps from (a) to (f) to form a plurality of second memory cell arrays over the second memory cell array.

13. A mask read-only-memory structure, comprising:

a substrate;

gate dielectric over the substrate;

a plurality of first conductive strips over the gate dielectric layer;

a first dielectric layer over the substrate and the first conductive strips, wherein the first dielectric layer has a plurality of first coding openings and that each first coding openings expose the first conductive strip;

a plurality of first wells each located inside the first conductive strip at the bottom of the first coding opening; and

a plurality of second conductive strips over the first dielectric layer and inside the first coding openings, wherein the second conductive strips connect electrically with their respective first wells, and that the gate dielectric layer, the first conductive strips, the first dielectric layer, the first wells, the second conductive strips together form a first memory cell array.

14. The structure of claim 13, wherein material constituting the first conductive strips includes N+ doped polysilicon/Silicide/N+ doped polysilicon.

15. The structure of claim 13, wherein the first conductive strips have a doping state that differs from the doping state of the first wells.

16. The structure of claim 13, wherein material constituting the second conductive strips is selected from a group consisting of aluminum, tungsten, copper and doped polysilicon.

17. The structure of claim 13, wherein the first conductive strips are aligned in a direction perpendicular to the second conductive strips.

18. The structure of claim 13, wherein the mask ROM structure may further include a word line between each gate oxide layer and each first conductive strip.

19. The structure of claim 13, wherein the mask ROM structure may further include:

a second dielectric layer over the first dielectric layer and the second conductive strips;

a plurality of third conductive strips over the second dielectric layer;

a third dielectric layer over the second dielectric layer and the third conductive strips, wherein the third dielectric layer has a plurality of second coding openings and that each second coding opening exposes the third conductive strip;

a second well in the third conductive strip at the bottom of each second coding opening; and

a plurality of fourth conductive strips over the third dielectric layer and inside the coding openings, wherein the fourth conductive strips connect electrically with the respective second wells such that the second dielectric layer, the third conductive strips, the third dielectric layer, the second wells, the fourth conductive strips together form a second memory cell array.

20. The structure of claim 19, wherein material constituting the third conductive strips includes doped polysilicon.

21. The structure of claim 19, wherein the third conductive strips have a doping state (N+ type) that differs from the doping state of the second wells (P+ type).

22. The structure of claim 19, wherein material constituting the fourth conductive strips is selected from a group consisting of aluminum, tungsten, copper and doped polysilicon.

23. The structure of claim 19, wherein the third conductive strips are aligned in a direction perpendicular to the fourth conductive strips.

24. The structure of claim 19, wherein the mask ROM structure may further include a plurality of second memory cell arrays stacked over the second memory cell array.

25. A method of decoding a mask read-only-memory (ROM), wherein the mask ROM at least includes a plurality of word lines, a plurality of wells over the respective word lines such that the word lines have a doping state (N+ type) that differs from the wells (P+ type) and a plurality of bit lines such that the bit lines are aligned in a direction perpendicular to the word lines and that the bit lines and the word lines are on separate planes, and some of the junctions between the bit line and the word line are electrically connected to corresponding well, the decoding method includes:

applying a first voltage to the bit line corresponding to a decoding location while applying a second voltage to all other bit lines such that the first voltage is greater than the second voltage, and at the same time, applying a third voltage to the word line corresponding to the decoding location while applying a fourth voltage to all the other word lines such that the fourth voltage is larger than the third voltage.