Oxidation process to improve polysilicon sidewall roughness

• US 6,794,313 B1
• Filed: 09/20/2002
• Issued: 09/21/2004
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Ming-Ching
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US10/251,327
• Time in Patent Office: 732 Days
• Field of Search: 438/669, 438/689, 438/770, 438/595
• US Class Current: 438/770
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/32137 of silicon-containing layers

Abstract

A new step is provided for the creation of polysilicon gate electrode structures. A layer of polysilicon is deposited over the surface of a layer of semiconductor material, the layer of polysilicon is etched using a layer of hardmask material for this purpose. The etch of the layer of polysilicon is performed using a dual power source plasma system. During the etching of the layer of polysilicon, a step of inert oxidation is inserted. This step forms a layer of passivation over the sidewalls of the etched layer of polysilicon. The step of inert oxidation is an oxygen-based plasma exposure.

Claims

1. A method of reducing surface roughness of sidewalls of a created gate electrode, comprising steps of:

providing a semiconductor substrate;

forming a layer of gate electrode material over said substrate;

initiating and partially completing etching said layer of gate electrode material;

then

initiating a step of oxidation of said partially etched layer of gate electrode material; and

continuing and completing patterning said layer of gate electrode material.

2. The method of claim 1, additionally removing a layer of gate oxide using said patterned layer of gate electrode material as a mask.

3. The method of claim 2, said layer of gate oxide comprising silicon dioxide.

4. The method of claim 3, said silicon dioxide being thermally grown in an oxygen-steam ambient at a temperature between 800 and 1,000 degrees C. to a thickness of between about 30 to 300 Angstrom.

5. The method of claim 2, wherein said layer of gate oxide is a composite oxide.

6. The method of claim 2, said layer of gate oxide being created by oxidation in a dry oxygen and anhydrous hydrogen chloride in an atmospheric or low pressure environment.

7. The method of claim 2, said layer of gate oxide being created by applying dry or wet oxidation with a NH₄/N₂O anneal at a temperature between about 650 and 950 degrees C.

8. The method of claim 2, said layer of gate oxide being created by Rapid Thermal Oxidation (RTO) of the surface of said substrate at a temperature between about 400 and 1,000 degrees C.

9. The method of claim 1, additionally removing a patterned layer of hardmask material from said patterned layer of gate electrode material.

10. The method of claim 9, said hardmask material comprising silicon dioxide obtained from TEOS, said TEOS being deposited by CVD or PECVD to a thickness of about 100 to about 1,000 Angstrom.

11. The method of claim 1, said gate electrode material comprising polysilicon.

12. The method of claim 11, said polysilicon being deposited to a thickness between about 200 and 5,000 Angstrom.

13. The method of claim 1, said step of oxidation comprising an oxygen based plasma exposure.

14. The method of claim 13, said oxygen based plasma exposure comprising applying a temperature of between about 180 and 210 degrees C. for a time between about 12 and 13 minutes, performed at a power of about 500 Watt, a pressure of about 800 mTorr, using O₂ as a source at a flow rate of about 500 sccm for about 15 minutes, said plasma being activated when the temperature rises above about 80 degrees C.

15. The method of claim 1, said etching said layer of gate electrode material and said oxidation being performed in a dual power source plasma system.

16. The method of claim 1, said gate material comprising polysilicon germanium.

17. The method of claim 16, said polysilicon germanium being deposited to a thickness between about 200 and 5,000 Angstrom.

18. The method of claim 1, said forming a layer of gate electrode material over said substrate comprising steps of:

successively creating over said substrate first a layer of gate oxide over which a layer of gate electrode material is deposited over which a layer of hardmask material is deposited; and

patterning said layer of hardmask material, creating an etch mask for etching said layer of gate electrode material.

19. The method of claim 1, said continuing and completing patterning said layer of gate electrode material comprising concurrently continuing said step of oxidation, creating an etched layer of gate electrode material over sidewalls of which a layer of oxide has been deposited.

20. A method of reducing surface roughness of sidewalls of a gate electrode, comprising steps of:

providing a semiconductor substrate, said substrate having been provided with first a layer of gate electrode oxide over the surface thereof over which second a layer of gate electrode material has been deposited over which third a mask of hardmask material has been created;

initiating and partially completing etching said layer of gate electrode material in accordance with said mask of hardmask material using a dual power source plasma system;

then

initiating a step of oxidation using said dual power source plasma system; and

continuing and completing etching said layer of gate electrode material while concurrently continuing said step of oxidation, creating an etched layer of gate electrode material over sidewalls of which a layer of oxide has been deposited.

21. The method of claim 20, additionally removing said layer of gate oxide using said etched layer of gate electrode material and said mask of hardmask material as a mask.

22. The method of claim 20, additionally removing said mask of hardmask material.

23. The method of claim 20, said gate electrode material comprising polysilicon.

24. The method of claim 23, said polysilicon being deposited to a thickness between about 200 and 5,000 Angstrom.

25. The method of claim 20, said step of oxidation comprising an oxygen based plasma exposure.

26. The method of claim 25, said oxygen based plasma exposure comprising applying a temperature of between about 180 and 210 degrees C. for a time between about 12 and 13 minutes, performed at a power of about 500 Watt, a pressure of about 800 mTorr, using O₂ as a source at a flow rate of about 500 sccm for about 15 minutes, said plasma being activated when the temperature rises above about 80 degrees C.

27. The method of claim 20, said hardmask material comprising silicon dioxide obtained from TEOS, said TEOS being deposited by CVD or PECVD to a thickness of about 100 to about 1,000 Angstrom.

28. The method of claim 20, said gate electrode material comprising polysilicon germanium.

29. The method of claim 28, said polysilicon germanium being deposited to a thickness between about 200 and 5,000 Angstrom.

30. The method of claim 20, said layer of gate oxide comprising silicon dioxide.

31. The method of claim 30, said silicon dioxide being thermally grown in an oxygen-steam ambient at a temperature between 800 and 1,000 degrees C. to a thickness of between about 30 to 300 Angstrom.

32. The method of claim 20, wherein said layer of gate oxide is a composite oxide.

33. The method of claim 20, said layer of gate oxide being created by oxidation in a dry oxygen and anhydrous hydrogen chloride in an atmospheric or low pressure environment.

34. The method of claim 20, said layer of gate oxide being created by applying dry or wet oxidation with a NH₄/N₂O anneal at a temperature between about 650 and 950 degrees C.

35. The method of claim 20, said layer of gate oxide being created by Rapid Thermal Oxidation (RTO) of said substrate at a temperature between about 400 and 1,000 degrees C.

36. A method of reducing roughness in sidewalls of a polysilicon gate electrode, comprising steps of:

providing a semiconductor substrate, said substrate having been provided with first a layer of gate oxide over the surface thereof over which second a layer of polysilicon has been deposited over which third a mask of hardmask material has been created;

initiating and partially completing etching said layer of polysilicon in accordance with said mask of hardmask material using a dual power source plasma system;

initiating a step of oxidation using said dual power source plasma system; and

continuing and completing etching said layer of polysilicon while concurrently continuing said step of oxidation, creating an etched layer of polysilicon over sidewalls of which a layer of oxide has been deposited.

37. The method of claim 36, additionally removing said layer of gate oxide using said mask of hardmask material and said etched layer of polysilicon as a mask.

38. The method of claim 36, additionally removing said mask o f hardmask material.

39. The method of claim 36, said layer of polysilicon being deposited to a thickness between about 200 and 5,000 Angstrom.

40. The method of claim 36, said step of oxidation comprising an oxygen based plasma exposure.

41. The method of claim 40, said oxygen based plasma exposure comprising applying a temperature of between about 180 and 210 degrees C. for a time between about 12 and 13 minutes, performed at a power of about 500 Watt, a pressure of about 800 mTorr, using O₂ as a source at a flow rate of about 500 sccm for about 15 minutes, said plasma being activated when the temperature rises above about 80 degrees C.

42. The method of claim 36, wherein said hardmask material is silicon dioxide obtained from TEOS, said TEOS being deposited by CVD or PECVD to a thickness of about 100 to about 1,000 Angstrom.

43. A method of reducing surface roughness in sidewalls of a polysilicon gate electrode, comprising steps of:

providing a semiconductor substrate, said substrate having been provided with first a layer of gate oxide over the surface thereof over Which second a layer of polysilicon has been deposited over which third a mask of hardmask material has been created;

initiating and partially completing etching said layer of polysilicon in accordance with said mask of hardmask material using a dual power source plasma system;

initiating a step of oxidation comprising an oxygen based plasma exposure using said dual power source plasma system; and

continuing and completing etching said layer of polysilicon while concurrently continuing said step of oxidation, creating an etched layer of polysilicon over sidewalls of which layers of oxide have been deposited.

44. The method of claim 43, additionally removing said layer of gate oxide using said mask of hardmask material and said etched layer of polysilicon as a mask.

45. The method of claim 43, additionally removing said mask of hardmask material.

46. The method of claim 43, said layer of polysilicon being deposited to a thickness between about 200 and 5,000 Angstrom.

47. The method of claim 43, said oxygen based plasma exposure comprising applying a temperature of between about 180 and 210 degrees C. for a time between about 12 and 13 minutes, performed at a power of about 500 Watt, a pressure of about 800 mTorr, using O₂ as a source at a flow rate of about 500 sccm for about 15 minutes, said plasma being activated when the temperature rises above about 80 degrees C.

48. The method of claim 43, said hardmask material preferably comprising silicon dioxide obtained from TEOS, said TEOS being deposited by CVD or PECVD to a thickness of about 100 to about 1,000 Angstrom.