Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation

• US 6,794,904 B2
• Filed: 10/29/2002
• Issued: 09/21/2004
• Est. Priority Date: 05/26/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishikawa, Masatoshi, Ooishi, Tsukasa
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/281,951
• Publication Number:
  US 20030038653A1
• Time in Patent Office: 693 Days
• Field of Search: 326/101-103, 257/371, 257/372
• US Class Current: 326/103
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Claims

1. A semiconductor integrated circuit device having a logic gate, comprising:

a semiconductor substrate;

a plurality of first active regions formed on said semiconductor substrate, each constituting a source/drain of a transistor forming said logic gate;

a second active region formed on said semiconductor substrate to be located at either side of a periphery of said plurality of first active regions; and

an insulating region formed on said semiconductor resistance insulating respective ones of said plurality of first active regions and said second active region from one another;

wherein

at least any of said plurality of first active regions has a difference in length in the longitudinal direction perpendicular to the side of said second active region, and said second active region has a portion opposing any of said plurality of first active regions having a shorter length in the longitudinal direction, said portion projecting to be in a close proximity to said first active region having the shorter length.

2. The semiconductor integrated circuit device according to claim 1, wherein

said projecting portion of said second active region extending into a region between ones of said plurality of first active regions each having a longer length in the longitudinal direction.

3. The semiconductor integrated circuit device according to claim 1, further comprising:

a gate insulating film formed on at least a portion of said second active region; and

a gate electrode formed on said gate insulating film.

4. The semiconductor integrated circuit device according to claim 3, wherein

said second active region, said gate insulating film formed on said second active film, and said gate electrode formed on said gate insulating film constitute an MOS configuration.

5. The semiconductor integrated circuit device according to claim 4, wherein

said gate electrode and said second active region constituting said MOS configuration are electrically connected to a first power supply and a second power supply, respectively.

6. The semiconductor integrated circuit device according to claim 5, wherein

said gate electrode and said second active region functioning decoupling capacitance of a power supply.

7. The semiconductor integrated circuit device according to claim 6, further comprising a memory array, wherein

said decoupling capacitance is formed in a circuit arrangement in said memory array.

8. The semiconductor integrated circuit device according to claim 6, further comprising a circuit portion constituting a hierarchical power supply line, wherein

said decoupling capacitance is formed in a logic gate portion of said circuit portion.

9. A semiconductor integrated circuit device having a logic gate comprising:

a semiconductor substrate;

a plurality of first active regions formed on said semiconductor substrate each constituting a source/drain of a transistor farming said logic gate;

a second active region formed on said semiconductor substrate to be located at either side of a periphery of said plurality of first active regions; and

an insulating region formed on said semiconductor substrate insulating respective ones of said plurality of first active regions and said second active region from one another;

a gate insulating film formed on said first and second active regions and said insulating region;

a plurality of first gate wirings formed on said gate insulating film to correspond to said plurality of first active regions, each constituting a gate of said transistor; and

a second gate wiring formed on said gate insulating film to correspond to said second active region, wherein

at least any of said plurality of first gate wirings has a difference in length in the longitudinal direction perpendicular to the side of said second gate wiring, and said second gate wiring has a portion opposing any of said plurality of first gate wirings having a shorter length in the longitudinal direction, said portion projecting to be in close proximity to said first gate wiring having at the shorter length.

10. The semiconductor integrated circuit device according to claim 9, wherein

said projecting portion of said second gate wiring extending into a region between ones of said plurality of first gate wirings each having a longer length in the longitudinal direction.

11. The semiconductor integrated circuit device according to claim 9, wherein

said second gate wiring and said second active region are electrically connected to a first power supply and a second power supply, respectively.

12. The semiconductor integrated circuit device according to claim 9, further comprising a power supply line formed at an upper layer on said second gate wiring, said power supply line being from a power supply different from said first power supply, wherein

said second gate wiring and said power supply line constitute a parallel plate capacitor.

13. A semiconductor integrated circuit device having a logic gate, comprising:

a semiconductor substrate;

a plurality of active regions formed on said semiconductor substrate, each constituting a source/drain of a transistor forming said logic gate, said plurality of active regions including an active region of a first conductivity type and an active region of a second conductivity type; and

an insulating region formed on said semiconductor substrate insulating respective ones of said plurality of active regions from one another, wherein

a well of said first conductivity type is formed in the portion under said active region of said second conductivity type.