Radiation-hard circuit

• US 6,794,908 B2
• Filed: 05/30/2003
• Issued: 09/21/2004
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Erstad, David O.
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/452,557
• Publication Number:
  US 20040022005A1
• Time in Patent Office: 480 Days
• Field of Search: 327/108, 327/112, 327/427, 327/436, 327/437, 327/534, 327/537, 327/581, 327/576, 327/566, 327/206, 326/9, 326/10, 326/13, 326/83, 326/271, 326/102-104, 257/369, 257/371
• US Class Current: 327/112
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits

Abstract

A radiation hardening circuit that includes two series-connected transistors that can replace any single transistor in a circuit. The hardening circuit includes a resistor that has a first node and a second node, a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The first node of the resistor may be conductively connected to the drain terminal of the first transistor and the second node of the resistor is conductively connected to the body terminal of the first transistor. The hardening circuit also includes a second transistor in series with the first transistor, driven so that both transistors are off or on at any given time. The circuit is resistant to radiation-induced events due to the body bias of the first transistor, the off state of the second transistor, and the current limiting effect of the resistor.

Claims

1. A radiation-hardening circuit comprising:

a first transistor of a given transistor type having a source terminal, a gate terminal, a drain terminal, and a body terminal;

a resistor having a first node and a second node, wherein the first node of the resistor is conductively coupled to an output node and wherein the second node of the resistor is conductively coupled to the body terminal of the first transistor, the body terminal of the first transistor having no further connection to any gate, drain, source, or body terminal of any other transistor; and

a second transistor of a same transistor type as the first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the second transistor is conductively coupled to the source terminal of the first transistor and the gate terminal of the second transistor is conductively coupled to the gate terminal of the first transistor.

2. The circuit of claim 1, wherein the output node is the drain terminal of the first transistor.

3. The circuit of claim 1, wherein the first transistor and the second transistor are N-channel field effect transistors (FETs).

4. The circuit of claim 2, wherein the first transistor and the second transistor are N-channel FETs.

5. The circuit of claim 3, wherein the first transistor and the second transistor in combination replace any single N-channel FET for which hardening is required.

6. The circuit of claim 1, wherein the first transistor and the second transistor are P-channel FETs.

7. The circuit of claim 2, wherein the first transistor and the second transistor are P-channel FETs.

8. The circuit of claim 6, wherein the first transistor and the second transistor in combination replace any single P-channel FET for which hardening is required.

9. The circuit of claim 3, wherein the source terminal of the second transistor is conductively coupled to a reference potential, and wherein the drain terminal of the first transistor comprises the output of the circuit.

10. The circuit of claim 4, wherein the source terminal of the second transistor is conductively coupled to a reference potential, and wherein the drain terminal of the first transistor comprises the output of the circuit.

11. The circuit of claim 6, wherein the source terminal of the second transistor is conductively coupled to a reference potential, and wherein the drain terminal of the first transistor comprises the output of the circuit.

12. The circuit of claim 7, wherein the source terminal of the second transistor is conductively coupled to a reference potential, and wherein the drain terminal of the first transistor comprises the output of the circuit.

13. A radiation-hardening inverter circuit comprising:

a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal;

a first resistor having a first node and a second node, wherein the first node of the first resistor is conductively coupled to the drain terminal of the first transistor and the second node of the first resistor is conductively coupled to the body terminal of the first transistor, the body terminal of the first transistor having no further connection to any gate, drain, source, or body terminal of any other transistor;

a second transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the second transistor is conductively coupled to the source terminal of the first transistor and the gate terminal of the second transistor is conductively coupled to the gate terminal of the first transistor;

a third transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the third transistor is conductively coupled to the drain terminal of the first transistor, the drain terminal of the third transistor comprising the sole output of the inverter circuit;

a second resistor having a first node and a second node, wherein the first node of the second resistor is conductively coupled to the drain terminal of the third transistor and the second node of the second resistor is conductively coupled to the body terminal of the third transistor, the body terminal of the third transistor having no further connection to any gate, drain, source, or body terminal of any other transistor; and

a fourth transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the fourth transistor is conductively coupled to the source terminal of the third transistor and the gate terminal of the fourth transistor is conductively coupled to the gate terminal of the third transistor, and to the gate terminals of the first and second transistors, the interconnected gate terminals comprising the input of the inverter circuit.

14. A radiation-hardening circuit comprising:

a first transistor of a given transistor type having a source terminal, a gate terminal, a drain terminal, and a body terminal;

a resistor having a first node and a second node, wherein the first node of the resistor is conductively coupled to the drain terminal of the first transistor and wherein the second node of the resistor is conductively coupled to the body terminal of the first transistor, the body terminal of the first transistor having no further connection to any gate, drain, source, or body terminal of any other transistor; and

a second transistor of a same transistor type as the first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal;

wherein the drain terminal of the second transistor is conductively coupled to the source terminal of the first transistor, the gate terminal of the second transistor is conductively coupled to the gate terminal of the first transistor, and wherein the body terminal of the second transistor is conductively coupled to the source of the second transistor.

15. A radiation-hardening circuit comprising:

a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal;

a first resistor having a first node and a second node, wherein the first node of the first resistor is conductively coupled to the drain terminal of the first transistor and the second node of the first resistor is conductively coupled to the body terminal of the first transistor, the body terminal of the first transistor having no further connection to any gate, drain, source, or body terminal of any other transistor;

a second transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the second transistor is conductively coupled to the source terminal of the first transistor, the gate terminal of the second transistor is conductively coupled to the gate terminal of the first transistor, and the body terminal of the second transistor is conductively coupled to a reference node;

a third transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein the drain terminal of the third transistor is conductively coupled to the source terminal of the second transistor;

a second resistor having a first node and a second node, wherein the first node of the second resistor is conductively coupled to the drain terminal of the first transistor and the second node of the second resistor is conductively coupled to the body terminal of the third transistor, the body terminal of the third transistor having no further connection to any gate, drain, source, or body terminal of any other transistor; and

a fourth transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal, wherein;

the drain terminal of the fourth transistor is conductively coupled to the source terminal of the third transistor;

the gate terminal of the fourth transistor is conductively coupled to the gate terminal of the third transistor, and to the gate terminals of the first and second transistors, the interconnected gate terminals comprising the input of the circuit;

the source terminal of the fourth transistor is conductively coupled to the reference node; and

the body terminal of the fourth transistor is conductively coupled to the source terminal of the fourth transistor.