High gain wideband driver amplifier

• US 6,794,934 B2
• Filed: 12/14/2001
• Issued: 09/21/2004
• Est. Priority Date: 12/14/2001
• Status: Expired due to Fees

• Current Assignee: iTerra Communications LLC (Renesas Electronics Corporation)
• Original Assignee: iTerra Communications LLC (Renesas Electronics Corporation)
• Inventors: Betti-Berutto, Andrea, DʼAgostino, Stefano
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/022,012
• Publication Number:
  US 20030112075A1
• Time in Patent Office: 1,012 Days
• Field of Search: 330/53, 330/54, 330/69, 330/84, 330/124.R, 330/253, 330/286, 330/295, 330/301, 330/308
• US Class Current: 330/124.00R
• CPC Class Codes: H03F 1/18 by use of distributed coupling , i.e. distributed amplifiers distributed amplifiers using coupling networks with distributed constants H03F3/605
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 3/1935 with junction-FET devices
• CPC Class Codes: H03F 3/607 using FET's

Abstract

Methods and circuitry for implementing monolithic high gain wideband amplifiers. The invention implements an amplifier with a limiter that also performs a signal dividing function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive two gate input lines of a combiner distributed amplifier.

Claims

1. An amplifier circuit comprising:

a limiter preamplifier including;

a differential amplifier coupled to receive a differential input signal at its inputs, and configured to generate a differential output signal made up of a first output signal and a second output signal, and

an output state having a first differential output amplifier coupled to the first output signal and a second differential output amplifier coupled to the second output signal; and

a combiner distributed amplifier having a first input coupled to a first output of the first differential output amplifier, and a second input coupled to a first output of the second differential output amplifier,

wherein the output of the first differential output amplifier and the output of the second differential output amplifier are of the same phase.

2. The amplifier circuit of claim 1 further comprising:

a first level shift circuit coupled between the first output of the first differential output amplifier and the first input of the combiner distributed amplifier; and

a second level shift circuit coupled between the first output of the second differential output amplifier and the second input of the combiner distributed amplifier.

3. The amplifier circuit of claim 2 wherein the differential amplifier of the limiter preamplifier comprises a plurality of serially-coupled differential amplifier cells configured to amplify and limit a level of the differential input signal.

4. The amplifier circuit of claim 3 wherein each of the first and second level shift circuitry corn rises a plurality of serially-coupled diodes.

5. The amplifier circuit of claim 1 wherein the first differential output amplifier comp as a first input coupled to the first output signal, a second input that is resistively terminated, and a second output that is 180 degrees out of phase with respect to the first output of the firs differential output amplifier, the second output being resistively terminated.

6. The amplifier circuit of claim 5 wherein the second differential output amplifier comp es a first input coupled to the second output signal, a second input that is resistively terminated, and a second output that is 180 degrees out of phase with respect to the first output of the second differential output amplifier, the second output being resistively terminated.

7. The amplifier circuit of claim 1 wherein the differential amplifier comprises:

a differential input age having first and second inputs coupled to receive the differential input signal; and

a buffer output stag coupled to the differential input stage and configured to shift a signal level at an output of the differential input stage.

8. The amplifier circuit of claim 7 wherein the buffer output stage in the differential amplifier comprises:

a first source-follow or transistor coupled at a first output of the differential input stage;

a plurality of serially-coupled diodes coupled between a source terminal of the first source-follower transistor and the first output signal;

a second source-follower transistor coupled at a second output of the differential input stage; and

a plurality of serially-coupled diodes coupled between a source terminal of the second source-follower transistor and the second output signal.

9. The amplifier circuit of claim 1 wherein each of the first and the second differential output amplifiers comprises:

a first field-effect transistor having a gate terminal forming a first input node, a drain terminal forming a first output node, and a source terminal coupled to a common source node;

a second field-effect transistor having a gate terminal forming a second input node, a drain terminal forming a second output node, and a source terminal coupled to the common source node;

a first load device coupled between the first output node and a high power supply;

a second load device coupled between the second output node and the high power supply; and

a current-source device coupled between the common source node and a low power supply.

10. The amplifier circuit of claim 9 wherein each of the first and the second load device comprises a resistor coupled in series to an inductor.

11. The amplifier circuit of claim 9 wherein the first output node in each of the first and second differential amplifiers is a non-inverting node, and the second output node is an invention node.

12. The amplifier circuit of claim 11 wherein the first input of the combiner distributed amplifier couples to the non-inverting node of the first differential output amplifier, and the second input of the combiner distributed amplifier couples to the inverting node of the second differential output amplifier.

13. The amplifier circuit of claim 12 wherein the load device coupled to the non-inverting node of the first differential output amplifier comprises a resistor coupled to an inductor, while the load device coupled to the inverting node of the first differential output amplifier is eliminated providing for a short between the inverting node of the first differential output amplifier and the high power supply.

14. The amplifier circuit of claim 12 wherein the load device coupled to the inverting node of the second differential output amplifier comprises a resistor coupled to an inductor, while the load device coupled to the non-inverting node of the second differential output amplifier is eliminated providing for a short between the non-inverting node of the second differential output amplifier and the high power supply.

15. The amplifier circuit of claim 1 wherein the combiner distributed amplifier comprises:

a first plurality of transistor amplifier cells coupled in cascade having a common gate line coupled the first input of the combiner distributed amplifier, and a common drain line coupled to an output of the amplifier circuit; and

a second plurality of transistor amplifier cells coupled in cascade having a common gate line coupled to the second input of the combiner distributed amplifier, and a common drain line coupled to the output of the amplifier circuit.

16. The amplifier circuit of claim 15 wherein each of the transistor amplifier cells comprises a single common-source field-effect transistor.

17. The amplifier circuit of claim 15 wherein each of the transistor amplifier cello comprises a cascode-coupled pair of field-effect transistors.

20. A communication system comprising:

a receiver comprising;

an optical input circuit coupled to receive an optical signal and to convert the optical signal to an electrical signal,

a trans-impedance amplifier coupled to receive and amplify the electrical signal,

a limiter coupled to the trans-impedance amplifier; and

a demultiplexer coupled to receive an output of the limiter and configured to de-serialize the electrical signal into a plurality of lower frequency parallel signals to be transmitted to a signal processing unit; and

a transmitter comprising;

a multiplexer coupled to receive a plurality of parallel signals from the signal processing unit, and configured to serialize the parallel signals into a single differential signal;

the driver amplifier of claim 1, coupled to receive the differential signal and to generate an output signal; and

an optical modulator coupled to the driver amplifier and configured to convert the output signal into a modulated optical signal.

18. A method of amplifying a high frequency signal comprising:

receiving a differential signal at differential inputs of a limiter circuit;

performing a limiting function on the differential signal;

using the limiter circuit to amplify the differential signal and to generate a pair of in-phase output signals; and

applying, respectively, the pair of in-phase output signals to a pair of input terminals of a combiner distributed amplifier.

19. The method of claim 18 further comprising level shifting the pair of in-phase output signal before applying them to the pair of input terminals of the combiner distributed amplifier.

21. A limiter amplifier comprising:

a differential amplifier coupled to receive a differential signal at its inputs and configured to generate a differential output signal made up of a first signal and a second signal;

an output stage having a first differential output amplifier coupled to receive the first signal and a second differential output amplifier coupled to receive the second signal; and

a combiner distributed amplifier having a first input coupled to receive the first mingle-ended output signal of the first differential output amplifier, and a second input coupled to receive the second singe-ended output signal of the second differential output amplifier,

wherein, the first differential output amplifier comprises a first differential pair and is configured to generate a first single-ended output signal and the second differential output amplifier comprises a second differential pair and is configured to generate a second single-ended output signal that is in phase with the first single-ended output signal.

22. An amplifier circuit comprising:

a first differential amplifier having a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

a second differential amplifier having an input coupled to the non-inverting output of the first differential amplifier, and a non-inverting output;

a third differential amplifier having an input coupled to the inverting output of the first differential amplifier, and an veiling output;

a combiner distribute amplifier having a first input coupled to the non-inverting output of the second differential puffer and a second input coupled to the inverting output of the third differential amplifier,

wherein the input of the second differential amplifier and the input of the third differential amplifier are the same type of input, and

wherein the first duff signal amplifier, the second differential amplifier and the third differential amplifier each comprise a differential pair.

23. The amplifier circuit of claim 22 wherein input of the second differential amplifier and the input of the third differential amplifier are non-inverting inputs.

24. The amplifier circuit of claim 22 wherein input of the second differential amplifier and the input of the third differential amplifier are inverting inputs.