Integrator reset mechanism

• US 6,795,006 B1
• Filed: 07/18/2003
• Issued: 09/21/2004
• Est. Priority Date: 07/18/2003
• Status: Expired due to Fees

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: LeReverend, Remi, Delight, Guy
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US10/622,991
• Time in Patent Office: 431 Days
• Field of Search: 341/143, 341/172, 327/336, 327/554
• US Class Current: 341/143
• CPC Class Codes: G06G 7/1865 with initial condition setting
• CPC Class Codes: H03M 3/364 by resetting one or more loop filter stages
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Abstract

An integrator with a reset mechanism comprises an integration capacitor and a replacement integration capacitor, wherein the integration capacitor is replaced with the replacement integration capacitor during a reset operation. A method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method may further comprise temporarily removing the integration capacitor and replacing it with a reset capacitor multiple times during a single reset operation of the integrator.

Claims

1. An integrator circuit with a reset mechanism, comprising:

an integration capacitor;

a reset capacitor;

a first integration switch coupled between an input of said integrator and an input side of said integration capacitor;

a second integration switch coupled between an output side of said integration capacitor and an output of said integrator;

a third integration switch coupled between an input common mode voltage and an input side of said reset capacitor;

a fourth integration switch coupled between an output side of said reset capacitor and an output common mode voltage;

a first reset switch coupled between said input of said integrator and said input side of said reset capacitor,

a second reset switch coupled between said output side of said reset capacitor and said output of said integrator;

a third reset switch coupled between said input common mode voltage and said input side of said integration capacitor; and

a fourth reset switch coupled between said output side of said integration capacitor and said output common mode voltage, wherein said integration switches are closed during an integration mode and open during a reset mode, and wherein said reset switches are closed during said reset mode and open during said integration mode.

2. An integrator with a reset mechanism, comprising a replacement integration capacitor which replaces an integration capacitor during a reset mode of the integrator.

3. The integrator of claim 2, wherein said integration capacitor is charged to a predefined voltage during said reset mode.

4. A method of resetting an integrator comprising temporarily removing an integration capacitor and replacing said integration capacitor with a reset capacitor during a reset operation of said integrator.

5. The method of claim 4, further comprising charging said integration capacitor to a predefined voltage during said reset operation.

6. The method of claim 4, wherein temporarily removing said integration capacitor and replacing said integration capacitor with said reset capacitor is repeated one or more times.

7. A delta-sigma modulator having a plurality of integration stages, wherein at least one of said integration stages comprises a first capacitor for integration and a second capacitor to replace the first capacitor in resetting said at least one integration stage.

8. A differential integrator, comprising a pair of normal integration capacitors and a pair of reset integration capacitors, wherein said normal integration capacitors are rotated out of the integrator and the reset integration capacitors are rotated into the integrator to reset the integrator.

9. A circuit for resetting a state variable output of an integrator, comprising:

a plurality of integration switches, wherein said integrator operates in a normal mode when said plurality of integration switches are closed;

a plurality of reset switches, wherein said plurality of reset switches are open when said plurality of integration switches are closed; and

at least one reset capacitor, wherein said reset capacitor replaces an integration capacitor between an input and an output of said integrator when said plurality of reset switches are closed and said plurality of integration switches are open.

10. A microphone, comprising a circuit for resetting a state variable output of at least one integrator, wherein said at least one integrator comprises a first capacitor for integration and a second capacitor to replace the first capacitor in resetting said at least one integrator.

11. A microphone, comprising:

a transducer,

a delta-sigma modulator, coupled to said transducer; and

means for maintaining said delta-sigma modulator in a stable state.

12. The microphone of claim 11, wherein said means for maintaining said delta-sigma modulator in a stable state comprises a circuit for resetting a state variable output of an integrator of said delta-sigma modulator, comprising:

a plurality of integration switches, wherein said integrator operates in a normal mode when said plurality of integration switches are closed;

a plurality of reset switches, wherein said plurality of reset switches are open when said plurality of integration switches are closed; and

at least one reset capacitor, wherein said reset capacitor replaces an integration capacitor between an input and an output of said integrator when said plurality of reset switches are closed and said plurality of integration switches are open.

13. The microphone of claim 12, wherein said means for maintaining said delta-sigma modulator in a stable state further comprises a limiter, coupled between said transducer and said delta-sigma modulator.