Programmable random bit source

• US 6,795,837 B1
• Filed: 03/31/1999
• Issued: 09/21/2004
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/283,769
• Time in Patent Office: 2,001 Days
• Field of Search: 708/3, 708/250-251, 708/801, 380/46
• US Class Current: 708/3
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

According to one embodiment, a programmable random bit source is disclosed. The programmable random bit source includes a latch having a data input, a bias input and a clock input. In addition, the programmable random bit source includes a programmable voltage source coupled to the bias input of the latch and a first oscillator coupled to the data input of the latch to output a first oscillating signal. Further, the programmable random bit source includes a second oscillator coupled to the clock input of the latch circuit to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

Claims

1. A programmable random bit source comprising:

a latch having a data input, a bias input and a clock input;

a programmable voltage source coupled to the bias input of the latch;

a first oscillator coupled to the data input of the latch, the first oscillator to output a first oscillating signal; and

a second oscillator coupled to the clock input of the latch circuit, the second oscillator to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

2. The programmable random bit source of claim 1 wherein the programmable voltage source comprises:

a first flash memory cell;

a second flash memory cell; and

a differential amplifier having a first input coupled to the first flash memory cell, and a second input coupled to the second flash memory cell.

3. The programmable random bit source of claim 1 wherein the programmable voltage source comprises:

a first resistor;

a second resistor; and

a differential amplifier having a first input coupled to the first resistor, and a second input coupled to the second resistor.

4. The programmable random bit source of claim 1 wherein the programmable voltage source comprises a logic gate having:

a first pull-up transistor;

a first pull-down transistor; and

a second pull-up transistor coupled in parallel with the first pull-up transistor.

5. The programmable random bit source of claim 4 wherein the logic gate further comprises means for selectively enabling the second pull-up transistor.

6. The programmable random bit source of claim 1 wherein the programmable voltage source comprises a logic gate having:

a first pull-up transistor;

a first pull-down transistor; and

a second pull-down transistor coupled in parallel with the first pull-down transistor.

7. The programmable random bit source of claim 6 wherein the logic gate further comprises means for selectively enabling the second pull-down transistor.

8. The programmable random bit source of claim 1 wherein the latch has an adjustable trip point.

9. The programmable random bit source of claim 8 wherein the adjustable trip point of the latch is alterable by a voltage output by the programmable voltage source.

10. A programmable random bit source comprising:

a latch having a data input and a bias input;

a programmable voltage source coupled to the bias input of the latch;

a comparator having an output coupled to the data input of the latch;

a resistor-inductor-capacitor circuit coupled to an input of the comparator, and

a noise source coupled to the resistor-inductor-capacitor circuit.

11. The programmable random bit source of claim 10 wherein the latch has an alterable trip point.

12. A digital processing system comprising:

an encryption/decryption circuit comprising a random number generator having,

a latch having a data input, a bias input and a clock input;

a programmable voltage source coupled to the bias input of the latch;

a first oscillator coupled to the data input of the latch, the first oscillator to output a first oscillating signal; and

a second oscillator coupled to the clock input of the latch circuit, the second oscillator to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

13. The digital processing system of claim 12 wherein the programmable voltage source comprises:

a first flash memory cell;

a second flash memory cell; and

a differential amplifier having a first input coupled to the first flash memory cell, and a second input coupled to the second flash memory cell.

14. The digital processing system of claim 13 wherein the latch has an adjustable trip point, wherein the adjustable trip point of the latch is alterable by a voltage output by the programmable voltage source.

15. The computer of claim 12 wherein the encryption/decryption circuit to encode and decode messages transmitted and received by the computer using a cipher-based cryptographic method.

16. The computer of claim 15 wherein the cipher-based cryptographic method is a single key system.

17. The computer of claim 15 wherein the cipher-based cryptographic method is a public key/private key system.