Configurable serial bus to couple baseband and application processors

• US 6,795,877 B2
• Filed: 11/29/2001
• Issued: 09/21/2004
• Est. Priority Date: 11/29/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glenn, Scott C.
• Primary Examiner(s): Fleming, Fritz
• Assistant Examiner(s): Chen, Alan S.
• Application Number:
  US09/998,532
• Publication Number:
  US 20030101295A1
• Time in Patent Office: 1,027 Days
• Field of Search: 710/38, 710/66, 712/39, 712/35
• US Class Current: 710/36
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system includes an application processor and a baseband processor that may be configurable to communicate by the transfer of data in a hexadecimal format, an octal format or a decimal format in accordance with programmed bits in a register'"'"'s data field.

Claims

1. An apparatus, comprising:

a storage register to store first and second data values;

first, second, third and fourth data terminals to provide hexadecimal data from the data terminals in accordance with the first and second data values decoded to select four active terminals and the first, second and third terminals to provide octal data in accordance with the first and second data values decoded to select three active terminals;

a terminal to provide a clock signal, wherein the hexadecimal data is changed with the clock signal; and

a terminal to provide a strobe signal, wherein an identity of a register to output data is provided at the appropriate data terminals during the strobe signal.

2. The apparatus of claim 1 further comprising a terminal to receive a wait signal, wherein the hexadecimal data is not changed with the clock signal when the wait signal is received.

3. A device, comprising:

a storage register to store a data field value;

a second register to store data;

data terminals to provide data from the second register having a base value as determined by the data field value; and

a terminal to supply a strobe signal, wherein an identification value of a register to output data is provided on the data terminals during the strobe signal.

4. The device of claim 3, wherein octal data is provided from the data terminals in accordance with the data field value.

5. The device of claim 3, wherein hexadecimal data is provided from the data terminals in accordance with the data field value.

6. A method, comprising:

selecting data terminals from a group of data terminals to supply data;

supplying a clock signal from a first terminal;

supplying a strobe signal from a second terminal; and

providing data at the selected data terminals when the strobe signal is inactive, the data changing in accordance with the clock signal.

7. The method of claim 6, further comprising providing a third terminal that receives a wait signal that keeps the data provided at the data terminals from changing.

8. The method of claim 6, further comprising providing null data from the data terminals when a channel register that stores the data sent to the data terminals is empty.

9. The method of claim 8, further comprising supplying an identification value corresponding to the channel register from the selected data terminals when the strobe signal is active.