Microprocessor with selected partitions disabled during block repeat

• US 6,795,930 B1
• Filed: 11/20/2000
• Issued: 09/21/2004
• Est. Priority Date: 01/14/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Laurenti, Gilbert, Morchipont, Olivier, Ichard, Laurent
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US09/716,645
• Time in Patent Office: 1,401 Days
• Field of Search: 713/324, 713/323, 713/320, 713/208, 713/241
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.

Claims

1. A method for operating a digital system comprising a microprocessor having at least one portion partitioned into a plurality of partitions, wherein the method comprises the steps of:

fetching a sequence of instructions within an instruction pipeline of the microprocessor into an instruction buffer;

detecting a local block of instructions within the fetched sequence of instructions in the instruction buffer, wherein the local block comprises a local repeat instruction;

associating, with the local repeat instruction, a repeat profile parameter indicative of partition that is unneeded for the execution of the local block of instructions;

repetitively executing first and subsequent instances of the local block of instructions; and

for subsequent instances of the repetitively executing step, inhibiting operation of the at least one unneeded partition for the subsequent instances of the repetitively executing step responsive to the repeat profile parameter.

2. The method of claim 1, further comprising:

storing the repeat profile parameter in a repeat profile parameter register;

wherein the inhibiting operation comprises applying control signals, corresponding to the contents of the repeat profile parameter register, to the partitioned portion of the microprocessor.

3. The method of claim 1, wherein the partitioned portion of the microprocessor comprises an instruction decoder, such that each partition of the instruction decoder is associated with a group of instructions;

wherein the repeat profile parameter is indicative of at least a first group of instructions not contained within the local block of instructions; and

wherein the inhibiting step inhibits at least one partition of the instruction decoder corresponding to the first group of instructions.

4. The method of claim 3, wherein the inhibiting step comprises inhibiting a first partition of the instruction decoder associated with a first stage of the pipeline and inhibiting a second partition of the instruction decoder associated with a second stage of the instruction pipeline.

5. The method of claim 1, wherein the partitioned portion of the microprocessor comprises an instruction decoder, such that each partition of the instruction decoder is associated with a group of instructions;

further comprising;

identifying a group of instructions that are inherently forbidden from being executed during repetitive execution of the local block of instructions;

and wherein the inhibiting step comprises inhibiting operation of a partition of the instruction decoder corresponding to the forbidden group of instructions during subsequent instances of the repetitively executing step while a remainder of the instruction decoder decodes instructions in the local block of instructions.

6. The method of claim 1, wherein the partitioned portion comprises an instruction register of the microprocessor, partitioned in accordance with different instruction lengths;

wherein the retrieved repeat profile parameter indicates a maximum instruction length of instructions within the local block of instructions; and

wherein the step of inhibiting comprises inhibiting loading of one or more of the instruction register partitions in accordance with the maximum instruction length.

7. The method of claim 1, wherein the partitioned portion comprises the instruction pipeline, partitioned in accordance to parallel instruction execution;

wherein the retrieved repeat profile parameter indicates a maximum instruction parallelism of instructions within the local block of instructions; and

wherein the step of inhibiting comprises inhibiting one or more parallel instruction execution partitions.

8. The method of claim 1, wherein the partitioned portion comprises a portion of the microprocessor, partitioned in accordance to data types;

wherein the retrieved repeat profile parameter indicates one or more data types not used within the local block of instructions; and

wherein the step of inhibiting comprises inhibiting one or more data type partitions.

9. The method of claim 1, wherein the repeat profile parameter indicates that updating of status circuitry is not required within the block of instructions;

and

wherein the step of inhibiting comprises inhibiting updating of the status circuitry.

10. The method of claim 1, wherein the partitioned portion comprises address generation circuitry of the microprocessor, partitioned into a plurality of partitions accordance to address modes;

wherein the repeat profile parameter indicates one or more address modes not used within the local block of instructions; and

wherein the step of inhibiting comprises inhibiting one or more address generation partitions.

11. The method of claim 1, wherein the associating step comprises associating the repeat profile parameter with a prologue instruction for the local block;

and further comprising;

retrieving the repeat profile parameter prior to the first instance of the repetitively executing step; and

inhibiting operation of the at least one unneeded partition during the first instance of the repetitively executing step responsive to the repeat profile parameter.

12. The method of claim 1, wherein the associating step comprises:

in the first instance of the repetitively executing step, monitoring execution of the block of instructions to determine partitions of the portion of the microprocessor that are unneeded in the execution of the local block of instructions; and

then storing a repeat profile parameter corresponding to the result of the monitoring step.

13. The method of claim 1, wherein the local block of instructions comprises an inner loop nested within an outer loop;

and further comprising;

associating a first repeat profile parameter with the inner loop and associating a second repeat profile parameter with the outer loop; and

retrieving the first repeat profile parameter during execution of the inner loop and retrieving the second repeat profile parameter of the outer loop;

and wherein the step of inhibiting comprises inhibiting operation of a first partition of the microprocessor during execution of the inner loop, and inhibiting operation of a second partition of the microprocessor during execution of the outer loop.

14. The method of claim 1, further comprising the steps of:

interrupting the repetitively executing step to execute an interrupt service routine (ISR);

masking partition inhibition so that all partitions of the microprocessor are enabled;

executing the ISR; and

then unmasking partition inhibition and returning to the repetitively executing step.

15. The method of claim 14 wherein the step of masking partition inhibition comprises masking the repeat profile parameter.

16. The method of claim 11, further comprising the step of assembling a source code program to create the sequence of instructions comprising the block of instructions, the prologue instruction and the associated repeat profile parameter, wherein the step of assembling comprises the steps of:

creating an instruction table with an entry for each instruction executable by a selected microprocessor, such that the entry for each instruction includes a group pattern defining a group of instructions that includes that instruction;

transforming the source code into a sequence of instructions;

determining the initial instruction and the final instruction for the repeatable block of instructions associated with the prologue instruction;

combining a plurality of group patterns selected from the instruction table representative of each instruction in the block of instructions to form a repeat profile parameter; and

associating the repeat profile parameter with the prologue instruction.

17. A digital system comprising a pipelined microprocessor, wherein the microprocessor comprises:

an instruction buffer comprising a plurality of instruction buffer registers for storing a plurality of instructions;

an instruction decoder for decoding instructions received from the instruction buffer, the instruction decoder being controllably connected in a pipeline, wherein the instruction decoder is partitioned into a plurality of partitions according to a respective plurality of instruction groups, at least one of the partitions and operable to inhibit decoding of instructions responsive to an inhibit input; and

block repeat control circuitry for storing a repeat profile parameter associated with a local repeat instruction, the local repeat instruction corresponding to a block of instructions stored in the instruction buffer that are to be repetitively executed, and for selectively asserting the inhibit input to at least one of the partitions of the instruction decoder responsive to the repeat profile parameter indicating that a local block of instructions corresponds to an instruction group not decoded by the at least one of the partitions.

18. The digital system of claim 17, wherein the block repeat control circuitry comprises a repeat profile register for storing the repeat profile parameter, the repeat profile circuitry coupled to the inhibit input of the at least one instruction decoder partition.

19. The digital system of claim 17, wherein the instruction decoder is hierarchical, such that a first portion of the instruction decoder is associated with a first stage of the pipeline and a second portion of the instruction decoder is associated with a second stage of the pipeline;

and

wherein at least a first instruction decoder partition in the first portion of the instruction decoder has a first inhibit input connected to a first output of the repeat profile circuitry and at least a second instruction decoder partition in the second portion of the instruction decoder has a second inhibit input connected to a second output of the repeat profile circuitry.

20. The digital system of claim 17, wherein the repeat profile register is for storing a repeat profile parameter provided by a prologue instruction of the local block of instructions.

21. The digital system of claim 17, wherein the repeat profile register is for storing a repeat profile parameter provided by monitoring circuitry coupled to the instruction decoder, wherein the monitoring circuitry is operable to monitor the instruction decoder during a first iteration of a first local block of instructions and to thereby derive a first repeat profile parameter indicative of a least a first group of instructions not included within the first local block of instructions.

22. The digital system of claim 17, wherein the repeat profile register is for storing two repeat profile parameters representative of an inner local loop and an outer local loop, such that the instruction decoder is operable to inhibit decoding of a first instruction group during execution of the inner local loop and to inhibit decoding of a second instruction group during execution of the outer local loop.

23. The digital system of claim 17, wherein the pipeline comprises an instruction fetch stage for fetching instructions from a program memory for transfer into the instruction buffer;

and

wherein the block repeat control circuitry is operable to inhibit the instruction fetch stage subsequent to fetching the final instruction of the local block of instructions from the program memory into the instruction buffer.

24. The digital system of claim 17, wherein the instructions are of a variable length;

and

wherein the instruction register is operable to be partially inhibited in response to the repeat profile circuitry during execution of the local block of instructions.

25. The digital system of claim 17 being a cellular telephone, further comprising:

an integrated keyboard connected to the processor via a keyboard adapter;

a display, connected to the processor via a display adapter;

radio frequency (RF) circuitry connected to the processor; and

an aerial connected to the RF circuitry.