Fast frame error checker for multiple byte digital data frames

• US 6,795,946 B1
• Filed: 05/05/2000
• Issued: 09/21/2004
• Est. Priority Date: 03/07/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Aszkenasy, Ruben, Drummond-Murray, Justin A
• Primary Examiner(s): Ton, David
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US09/565,481
• Time in Patent Office: 1,600 Days
• Field of Search: 714/801, 714/807, 714/781, 714/776, 714/774, 714/758, 714/759, 714/52, 714/48, 714/800, 714/779, 714/712, 714/724
• US Class Current: 714/758
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00

Abstract

Apparatus for performing a cyclic redundancy code check on a binary digital signal consisting of a variable multiplicity (M) of data bytes comprises a buffer register for temporarily storing in succession segments each consisting of an integral number (N) of bytes. Each successive segment is loaded into a cyclic redundancy checker which produces a remainder after performing polynomial division of the digital signal. When the number of bytes of the digital signal in the last segment is less than the integral plurality (N) that last segment is padded with constant data. The signal is deemed valid if the remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with zero to (N−1) bytes of the constant data

Claims

1. An apparatus for performing a cyclic redundancy code check on a receivedbinary digital signal comprising a variable multiplicity (M) of data bytes, comprising means for temporarily storing in succession segments each comprising an integral plurality (N) of bytes and for loading each successive segment into a cyclic redundancy checker which produces a remainder after performing polynomial division of the received binary digital signal, means operable, when the number of bytes of the received binary digital signal in the last segment is less than said integral plurality (N), to pad that last segment only at its end with constant data prior to loading into the cyclic redundancy checker and means for determining whether said remainder matches any of a plurality of predetermined remainders each one of which corresponds to the operation of the cyclic redundancy checker on a valid digital signal padded with a different number from zero to (N−

1) bytes of the constant data.

2. An apparatus for performing a cyclic redundancy code check on a received input binary digital signal comprising a variable multiplicity (M) of data bytes, comprising:

a buffer register for holding a succession of segments each comprising an integral plurality (N) of bytes;

a cyclic redundancy code checker which is operative to receive said succession of segments and to perform division thereof by a selected polynomial, to produce a remainder;

means for loading segments of said received input binary digital signal in turn into said buffer register;

means for preloading said buffer register with constant data whereby when a last segment in said succession contains a number (X) of bytes of data of said received input binary digital signal and said number (X) is less than said integral plurality (N) the segment contains (N−

X) bytes of constant data provided only at the end of the last segment;

means for storing a plurality (N) of predetermined remainders each one corresponding to a remainder value for (X) being a different number from zero to (N−

1); and

means for determining whether said remainder corresponds to one of said plurality (N) of predetermined remainders.

3. An apparatus as in claim 2 wherein said received input digital signal is in serial form and said means for loading comprises a deserializer receiving the received input digital signal and loading each successive integral plurality of bytes of the input signal into the buffer register.

4. The apparatus as in claim 2 wherein said remainder comprises a multiplicity of bits less than the number of bits in one of said segments.

5. The apparatus as in claim 2 wherein said cyclic redundancy code checker receives said segments each in parallel form.

6. A method of performing cyclic redundancy code check on a received binary digital signal comprising a variable multiplicity (M) of data bytes, comprising:

temporarily storing in succession segments each comprising and integral plurality (N) of bytes;

loading each successive segment into a cyclic redundancy checker;

producing a remainder after performing polynomial division of the received binary digital signal;

when the number of bytes of the received binary digital signal in the last segment is less than said integral plurality (N), causing the padding of that last segment only at its end with constant data; and

determining whether said remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with a different number from zero to (N−

1) bytes of the constant data.

7. An apparatus for performing a cyclic redundancy code check on a received input data packet comprising a variable multiplicity (M) of data bytes and including a cyclic redundancy code whereby said cyclic redundancy code check produces, after a predetermined polynomial division, a non-zero remainder when said received input data packet is valid, comprising:

a cyclic redundancy checker for producing a remainder by performing said predetermined polynomial division;

a buffer register for temporarily storing in succession on segments each comprising an integral plurality (N) of bytes whereof N is less than M;

means for loading each successive segment into a cyclic redundancy checker;

means for causing the padding of the last segment only at its end with constant data, when the number of bytes of the data packet in the last segment is less the said integral plurality (N); and

means for determining whether the said remainder matches any of a plurality of predetermined remainders each corresponding to the operation of said cyclic redundancy checker on a valid data packet padded with a different number from zero to (N−

1) bytes respectively of the constant data.

8. The apparatus as in claim 7 wherein said received input data packet is in serial form and said means for loading comprises a deserializer receiving the received input data packet and loading each successive integral plurality of bytes of the received input data packet into the buffer register.

9. The apparatus as in claim 7 wherein said remainder comprises a multiplicity of bits less than the number of bits in one of said segments.

10. The apparatus as in claim 7 wherein said cyclic redundancy checker receives said segments each in parallel form.

11. Apparatus for performing a cyclic redundancy code check on a received input data packet comprising a variable multiplicity (M) of data bytes and including a cyclic redundancy code whereby said cyclic redundancy code check produces, after division thereof by a selected polynomial, a non-zero remainder when said packet is valid, said apparatus comprising:

a buffer register for holding a succession of segments each comprising an integral plurality (N) of bytes whereof N is less than M;

a cyclic redundancy code checker which is operative to receive said succession of segments and to perform division thereof by said selected polynomial, to produce a remainder;

means for loading segments of said input data packet in turn into said buffer register;

means for preloading said buffer register with constant data whereby when a last segment in said succession contains a number (X) of bytes of said data packet and said number (X) is less than said integral plurality (N) the segment contains (N−

X) bytes of constant data provided only at the end of the last segment;

means for storing a plurality (N) of predetermined remainders equal in number to said plurality (N) each ore corresponding to a remainder value for (X) being a different number from zero to (N−

1); and

means for determining whether the said remainder corresponds to one of said integral plurality (N) of predetermined remainders.

12. The apparatus as in claim 11 wherein said received input data packet is in serial form and said means for loading comprises a deserializer receiving the received input data packet and loading each successive integral plurality of bytes of the received input data packet into the buffer register.

13. A method for performing a cyclic redundancy code check on a received input data packet composed of a binary digital signal comprising a variable multiplicity (M) of data bytes and including a cyclic redundancy code whereby said cyclic redundancy code check produces, after a predetermined polynomial division, a non-zero remainder when said data packet is valid, comprising:

temporarily storing in succession segments each comprising an integral number (N) of bytes;

loading each successive segment into a cyclic redundancy checker;

producing a remainder after performing said polynomial division of the digital signal;

when the number of bytes of the digital signal in the last segment is less than said integral plurality (N), causing the padding of that last segment only at its end with constant data; and

determining whether said remainder matches any of a plurality of predetermined remainders each one of which corresponds to the operation of the cyclic redundancy checker on a valid digital signal padded with a different number from zero to (N−

1) bytes respectively of the constant data.

14. A method for performing a cyclic redundancy code check on a received binary digital signal comprising a variable multiplicity (M) of data bytes, comprising:

temporarily storing in succession segments each comprising an integral plurality (N) of bytes,

loading each successive segment into a cyclic redundancy checker;

producing a remainder after performing polynomial division of the received binary digital signal;

when the number of bytes of the received binary digital signal in the last segment is less than said integral plurality (N), causing the padding of that last segment with constant data which produces for said binary digital signal a respective predetermined remainder depending on the number of bytes of said constant data; and

determining whether said remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the cyclic redundancy checker on a valid digital signal padded with a different number from zero to (N−

1) bytes of the constant data.

15. An apparatus for performing a cyclic redundancy code check on a received input data packet comprising a variable multiplicity (M) of data bytes and including a cyclic redundancy code whereby said cyclic redundancy code check produces, after a predetermined polynomial division, a non-zero remainder when said received input data packet is valid, comprising:

a cyclic redundancy checker for producing a remainder by performing said predetermined polynomial division;

a buffer register for temporarily storing in succession segments each comprising an integral plurality (N) of bytes whereof N is less than M;

means for loading each successive segment into a cyclic redundancy checker;

means for causing the padding of the last segment with constant data which produces for said data packet a respective predetermined remainder depending on the number of bytes of said constant data, when the number of bytes of the data packet in the last segment is less than said integral plurality (N); and

means for determining whether the said remainder matches any of a plurality of predetermined remainders each corresponding to the operation of said cyclic redundancy checker on a valid data packet padded with a different number from zero to (N−

1) bytes respectively of the constant data.

16. The apparatus as in claim 15 wherein said received input data packet is in serial form and said means for loading comprises a deserializer receiving the received input data packet and loading each successive integral plurality of bytes of the received input data packet into the buffer register.

17. The apparatus as in claim 15 wherein said remainder comprises a multiplicity of bits less than the number of bits in one of said segments.

18. The apparatus as in claim 15 wherein said cyclic redundancy checker receives said segments each in parallel form.