Memory cell and method for forming the same

• US 6,797,573 B2
• Filed: 08/18/2003
• Issued: 09/28/2004
• Est. Priority Date: 06/21/2002
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Kris K.
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/643,269
• Publication Number:
  US 20040052139A1
• Time in Patent Office: 407 Days
• Field of Search: 438/300, 438/303, 438/329, 438/341, 438/363, 438/366, 438/413
• US Class Current: 438/300
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Claims

1. A method forming a semiconductor structure on a surface of a substrate, comprising:

forming an active region formed in the substrate;

forming an epitaxial post on the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;

forming a gate structure formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post; and

forming a capacitor formed on an exposed surface of the epitaxial post.

2. The method of claim 1 wherein forming the epitaxial post comprises:

forming first and second sacrificial structures spaced laterally apart on the substrate;

forming sidewalls on the first and sacrificial structures to define a trench region therebetween, the surface of the substrate exposed in the trench region;

forming an epitaxial layer on the exposed surface of the substrate in the trench region.

3. The method of claim 2 wherein forming the gate structure comprises:

removing the sidewalls on the first and second sacrifical structure to define gap between the sacrificial structures and the epitaxial post;

forming a gate oxide over exposed surface of the epitaxial post;

depositing polycystalline silicon in the gap region;

recessing the polycrystalline silicon below an upper surface of the epitaxial post; and

forming an insulating region on the polycystalline silicon in the gap between the polycrystalline silicon and the upper surface of the epitaxial post.

4. The method of claim 1 wherein forming the capacitor comprises:

forming a first layer of doped polycrystalline silicon on the surface opposite of the surface of the surface of the substrate of the epitaxial post;

diffusing dopants from the first layer of doped polycrystalline silicon to the epitaxial post;

forming a capacitor dielectric layer over the first layer of doped polycrystalline silicon; and

forming a second layer of doped polycrystalline silicon on the capacitor dielectric layer.

5. The method of claim 1, further comprising:

depositing an insulating interlayer over the gate structure;

opening a via through the insulating interlayer to expose a portion of the active region; and

depositing a conductive material over the insulating interlayer and into the opening to contact the exposed portion of the active region.

6. The method of claim 1 wherein forming the active region comprises forming buried digit lines in the substrate.

7. A method for forming pair of memory cells on a surface of the substrate, comprising:

forming an active region in the substrate;

forming a vertical transistor in an epitaxial post formed on the substrate surface and extending from the surface of the substrate, the vertical transistor further having a gate formed around a perimeter of the epitaxial post; and

forming a capacitor on the vertical transistor.

8. The method of claim 7 wherein forming the vertical transistor comprises:

forming a gate oxide on a surface defining the perimeter of the epitaxial post;

forming a gate on the gate oxide; and

forming insulating sidewalls on the gate.

9. The method of claim 7 wherein the forming the capacitor comprises forming a container shaped capacitor structure.

10. The method of claim 7, further comprising forming a diffusion region in the epitaxial post adjacent the capacitor.

11. The method of claim 7 wherein forming the active region comprises forming a buried digit line.

12. The method of claim 7, further comprising forming a digit line contact over the active region and proximate the vertical transistor.

13. The method of claim 7, further comprising forming an insulating region around the perimeter of the epitaxial post, and interposed between the capacitor and the vertical transistor.