Non-volatile dynamic random access memory

• US 6,798,008 B2
• Filed: 03/19/2003
• Issued: 09/28/2004
• Est. Priority Date: 03/19/2002
• Status: Expired due to Fees

• Current Assignee: 021C Incorporated
• Original Assignee: O2ic, Inc.
• Inventors: Choi, Kyu Hyun
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/394,407
• Publication Number:
  US 20040016947A1
• Time in Patent Office: 559 Days
• Field of Search: 257/298, 257/296, 257/300, 257/314, 257/315, 257/316, 257/317, 257/319, 365/185.08, 365/186.01
• US Class Current: 257/298
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.

Claims

1. A memory cell comprising:

an MOS transistor having a first current carrying terminal coupled to a first node, a second current carrying terminal coupled to a bitline associated with the memory cell, and a gate terminal coupled to a first terminal of the memory cell; and

a non-volatile device comprising;

a substrate region coupled to a second terminal of the memory;

a source region formed in the substrate region and coupled to the first node;

a drain region formed in the substrate region and separated from the source region by a first channel region;

said drain region being coupled to a third terminal of the memory cell;

a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer;

said first gate coupled to a fourth terminal of the memory cell; and

a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer;

wherein said first portion of the first channel region and said second portion of the channel do not overlap and wherein said second gate is coupled to a fifth terminal of the memory cell.

2. The memory cell of claim 1 wherein said first node has an active capacitor formed thereon.

3. The memory cell of claim 2 wherein the first node receive a voltage from the bitline and maintains the voltage after the MOS transistor is turned off.

4. The memory cell of claim 3 wherein the non-volatile device is adapted to store a charge representative of the voltage of the bitlines during a power-off cycle.

5. The memory cell of claim 4 wherein during the power-off cycle, the second terminal of the memory cell is adapted to receive the first voltage, the third terminal of the memory cell is adapted to receive a second voltage, the fourth terminal of the memory cell is adapted to receive a third voltage, and the fifth terminal of the memory cell is adapted to receive a fourth voltage.

6. The memory cell of claim 5 wherein the fourth voltage is greater than the first, second and third voltages.

7. The memory cell of claim 6 wherein the first voltage is 0 volt.

8. The memory cell of claim 6 wherein during the power-off cycle, the non-volatile devices traps electrons in its nitride layer.

9. The memory cell of claim 8 wherein the electrons are trapped via hot-electron injection.

10. The memory cell of claim 8 wherein after the power-off cycle, the first node stores charges it had prior to the power-off cycle.

11. The memory cell of claim 10 wherein after the power-off cycle, the first voltage is applied to the first and second terminals, the second voltage is applied to the third and fifth input terminals, and a fifth voltage is applied to the fourth terminal, wherein the fifth voltage is smaller than the second voltage.

12. The memory cell of claim 11 wherein the trapped electrons are untrapped by applying the first voltage to first, second and third terminals of the memory cell, applying a negative voltage to the fifth terminal of the memory cell and by enabling the fourth terminal of the memory cell to float.

13. The memory cell of claim 9 wherein said MOS transistor is periodically turned on.

14. The memory cell of claim 1 wherein the MOS transistor is formed in the substrate of the non-volatile device.

15. The memory cell of claim 14 wherein said substrate is a p-type region formed in an n-well.

16. The memory cell of claim 1 wherein said first insulating layer comprises oxide and nitride layers.