Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

• US 6,798,009 B2
• Filed: 02/11/2003
• Issued: 09/28/2004
• Est. Priority Date: 10/06/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US10/361,986
• Publication Number:
  US 20030142564A1
• Time in Patent Office: 595 Days
• Field of Search: 257/295-310, 438/243, 438/366, 438/242, 438/396
• US Class Current: 257/301
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical

Abstract

A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Claims

1. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar; and

a second plate of the trench capacitor.

2. The memory cell of claim 1, wherein the second plate includes poly-silicon.

3. The memory cell of claim 1, and further including an ohmic contact that couples the second plate to a layer of semiconductor material.

4. A memory device, comprising:

an array of memory cells, wherein at least one cell includes;

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;

a second plate of the trench capacitor;

a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;

a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and

wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.

5. The memory device of claim 4, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

6. The memory device of claim 4, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

7. The memory device of claim 4, wherein the second plate of the trench capacitor comprises poly-silicon that is maintained at a constant potential.

8. The memory device of claim 4, wherein the pillar has a sub-micron width allowing substantially full depletion of the body region.

9. The memory device of claim 4, wherein the word lines are sub-lithographic.

10. A memory array comprising:

an array of memory cells, each memory cell including

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;

a second plate of the trench capacitor;

a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.

11. The memory array of claim 10, wherein the gates of the access transistors are each formed integral with one of the word lines.

12. The memory array of claim 10, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

13. The memory array of claim 10, wherein the second plate of the trench capacitor comprises poly-silicon that is maintained at a constant potential.

14. The memory array of claim 10, wherein the word lines have a width that is less than the minimum feature size, F, of a lithographic process.

15. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;

a second plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and

an ohmic contact that couples the second plate to a layer of semiconductor material.

16. The memory cell of claim 15, wherein the second plate includes poly-silicon.

17. The memory cell of claim 15, wherein the ohmic contact includes a refractory metal.

18. A memory device, comprising:

an array of memory cells, wherein at least one cell includes;

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;

a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;

an ohmic contact that couples the second plate to a layer of semiconductor material;

a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;

a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and

wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.

19. The memory device of claim 18, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

20. The memory device of claim 18, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

21. The memory device of claim 18, wherein the second plate of the trench capacitor includes poly-silicon that is maintained at a constant potential.

22. The memory device of claim 18, wherein the pillar has a sub-micron width allowing substantially full depletion of the body region.

23. The memory device of claim 18, wherein the word lines are sub-lithographic.

24. A memory array comprising:

an array of memory cells, each memory cell including

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;

a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;

an ohmic contact that couples the second plate to a layer of semiconductor material;

a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.

25. The memory array of claim 24, wherein the gates of the access transistors are each formed integral with one of the word lines.

26. The memory array of claim 24, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

27. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;

a second polysilicon plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and

an ohmic contact that couples the second plate to a layer of semiconductor material.

28. The memory cell of claim 27, wherein the ohmic contact includes a refractory metal.