Technique for suppression of edge current in semiconductor devices

• US 6,798,034 B2
• Filed: 08/07/2002
• Issued: 09/28/2004
• Est. Priority Date: 04/20/2000
• Status: Expired due to Fees

• Current Assignee: Diglrad Corporation
• Original Assignee: Diglrad Corporation
• Inventors: Carlson, Lars S.
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/214,791
• Publication Number:
  US 20020185654A1
• Time in Patent Office: 783 Days
• Field of Search: 257/181, 257/478, 257/473, 257/471, 257/449, 257/288, 257/106, 257/299, 257/233, 257/428, 257/429, 257/430, 257/447, 257/448, 257/451, 257/452, 257/453, 257/455, 257/456, 257/457, 257/461, 257/459, 257/460, 257/454, 257/483, 257/420, 438/380
• US Class Current: 257/449
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 31/1121 Devices with Schottky gate
• CPC Class Codes: H01L 31/186 Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Claims

1. A photodiode array comprising:

a substrate having one or a plurality of gate regions and a bias electrode, wherein the substrate is terminated by one or more diced edges which diced edges represent surfaces of the substrate that were formed by dicing; and

a metal layer coating at least a portion of one of said surfaces of at least one of the diced edges, wherein the metal layer provides a Schottky barrier to suppresses injection of edge generation current into the substrate.

2. The photodiode array of claim 1, wherein the substrate is an n-type substrate.

3. The photodiode array of claim 2, wherein the metal layer is composed of platinum or palladium.

4. The photodiode array of claim 1, wherein the substrate is a p-type substrate.

5. The photodiode array of claim 4, wherein the metal layer is composed of titanium or aluminum.

6. The photodiode array of claim 1, wherein the metal layer coats all of the surface of the at least one of the diced edges.

7. The photodiode array of claim 1, wherein the metal layer is converted into a conducting, intermetallic layer by reaction with the substrate.

8. The photodiode array of claim 1, wherein the substrate includes a depletion region.

9. The photodiode of claim 8, wherein the metal layer suppresses the edge generation current outside the depletion region.

10. An array as in claim 1, wherein said diced edges are edges which are substantially perpendicular to a top surface of the substrate.