Thin stacked ball-grid array package

• US 6,798,057 B2
• Filed: 11/05/2002
• Issued: 09/28/2004
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bolkin, Todd O., Cobbley, Chad A.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/288,180
• Publication Number:
  US 20040084771A1
• Time in Patent Office: 693 Days
• Field of Search: 257/692-676, 257/773-737
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls on either side of each die and/or the interposer provide interconnects for stacking packages and also provide interconnects for module mounting. Each die may be electrically coupled to the interposer using wire bonds, “flip-chip” techniques, or other techniques as appropriate. A redistribution layer may also be formed on the outer surface of a bumped die to create connections between the die circuitry, ball pads and/or wire bonding pads. Because the two die are coupled to each other on opposite faces of the interposer, each package is extremely space-efficient. Individual packages may be stacked together prior to encapsulation or molding to further improve the stability and manufacturability of the stacked package.

Claims

1. A stackable semiconductor package comprising:

an interposer having two opposing sides;

two die, each die being attached to one of the two opposing sides of the interposer and being electrically coupled to the interposer by at least one wire interconnect;

a plurality of interface balls, each interface ball being electrically coupled to one of the die, wherein at least one of said interface balls is adjacent to a first side of said interposer and at least one of said interface balls is adjacent to a second side of said interposer, and

an encapsulating material disposed around the two die and the interposer, wherein at least a portion of each of the plurality of interface balls is exposed from the encapsulating material to form an external electrical interface to the two die.

2. The package of claim 1 further comprising a redistribution layer formed on a surface of each die opposite the interposer.

3. The package of claim 2 wherein the redistribution layer comprises an interface ball pad forming an interface between the die and one of the interface balls.

4. The package of claim 2 wherein the redistribution layer comprises a wire bond pad forming an interface between the die and one of the wire interconnects.

5. The package of claim 1 wherein the plurality of solder balls is disposed on the interposer, and wherein the interposer is configured to electrically couple each of the interface balls to one of the die.

6. A stacked semiconductor module comprising first and second stackable packages, wherein each stackable package comprises:

an interposer having two opposing sides;

two semi-conducting die, each die being coupled to one of the two opposing sides of the interposer and being electrically coupled to the interposer by at least one wire interconnect;

a plurality of solder balls, each solder ball being electrically coupled to one of the die, wherein at least one of said solder balls is adjacent to a first side of said interposer and at least one of said solder balls is adjacent to a second side of said interposer; and

an encapsulating material disposed around the two semi-conducting die and the interposer, wherein at least a portion of each of the plurality of solder balls is exposed from the encapsulating material to form an electrical interface to the two semi-conducting die; and

wherein each of a portion of the solder balls associated with the first stackable package is electrically coupled to one of the solder balls associated with the second stackable package to form an electrical connection therebetween.

7. The stacked semiconductor module of claim 6 wherein each of a second portion of the solder balls associated with the first stackable package is coupled to a printed circuit board.

8. The stacked semiconductor module of claim 7 wherein a third portion of the solder balls associated with the second stackable package is exposed from the stackable semiconductor package.

9. The stacked semiconductor module of claim 6 further comprising an underfill disposed between first and second stackable packages.

10. The stacked semiconductor module of claim 7 further comprising an underfill disposed between first and second stackable packages and between the first stackable package and the printed circuit board.

11. A stackable memory package comprising:

an interposer having two opposing sides;

two die, each die being mechanically coupled to one of the opposing sides by an adhesive, and wherein each die is electrically coupled to the interposer by a wire interconnect;

a plurality of interface balls, each of the interface balls being electrically coupled to at least one of the die, wherein at least one of said interface balls is adjacent to a first side of said interposer, and at least one of said interface balls is adjacent to a second side of said interposer; and

an encapsulate enclosing the two die but allowing at least a portion of each interface ball to protrude from the encapsulate.

12. A stackable memory package comprising:

an interposer having two opposing sides;

two semiconducting die, each die being mechanically coupled to one of the opposing sides by an adhesive, and wherein each die is electrically coupled to the interposer by a wire interconnect;

a plurality of solder balls, each ball being disposed upon the interposer to form an electrical connection between each ball and one of the die, wherein at least one of said interface balls is adjacent to a first side of said interposer, and at least one of said interface balls is adjacent to a second side of said interposer; and

an encapsulate enclosing the stackable memory package but allowing at least a portion of each solder ball to protrude from the encapsulate.

13. A stacked semiconductor module comprising first and second stackable packages, wherein each stackable package comprises:

a means for supporting two semi-conducting die in a face-to-face manner;

a plurality of means for providing an external electrical interface to one of the die;

means for electrically coupling the die to the plurality of providing means, and

means for encapsulating the two semi-conducting die such that at least a portion of each of the plurality of providing means is exposed from the encapsulating means to form an external electrical interface to the two semi-conducting die; and

wherein each of a portion of the plurality of providing means associated with the first stackable package is electrically coupled to one of the providing means associated with the second stackable package to form an electrical connection therebetween.