Chip structure and process for forming the same

• US 6,798,073 B2
• Filed: 01/06/2003
• Issued: 09/28/2004
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/337,668
• Publication Number:
  US 20030111711A1
• Time in Patent Office: 631 Days
• Field of Search: 257/778, 257/691, 257/692, 257/758, 257/759, 257/760
• US Class Current: 257/778
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip structure, comprising:

a substrate having a plurality of electric devices that are disposed on a surface of the substrate;

a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, the first interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the first interconnection scheme electrically connected to the electric devices, the first interconnection scheme including at least one first conductive pad and at least one second conductive pad, both the first conductive pad and the second conductive pad located on a surface of the first built-up layer, and the first conductive pad exposed to the outside; and

a second built-up layer arranged over the first built-up layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected with the first interconnection layer through the second conductive pad.

2. The chip structure according to claim 1, wherein the second built-up layer further includes a dielectric body and the second interconnection scheme interlaces inside the dielectric body of the second built-up layer.

3. The chip structure according to claim 2, wherein the dielectric body of the second built-up layer is made of an organic compound.

4. The chip structure according to claim 2, wherein the dielectric body of the second built-up layer is made of a macromolecule polymer.

5. The chip structure according to claim 2, wherein the dielectric body of the second built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

6. The chip structure according to claim 1, wherein at least one of the electric devices is an electrostatic discharge circuit and the electrostatic discharge circuit is electrically connected with the first interconnection scheme.

7. The chip structure according to claim 1, wherein at least one of the electric devices is a transition device, the transition device is electrically connected with the first interconnection scheme, a signal is transmitted from the transition device to the first interconnection scheme and then transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme and finally transmitted to the other one or more of the electric devices.

8. The chip structure according to claim 7, wherein the transition device is a driver, a receiver or an I/O circuit.

9. The chip structure according to claim 1, wherein the first interconnection scheme further includes at least one linking trace, through which the first conductive pad is electrically connected with the second conductive pad.

10. The chip structure according to claim 9, wherein the linking trace is shorter than 5,000 microns.

11. The chip structure according to claim 1, wherein the trace thickness of the second interconnection scheme is larger than that of the first interconnection scheme.

12. The chip structure according to claim 1, wherein the trace thickness of the second interconnection scheme ranges from 1 micron to 50 microns.

13. The chip structure according to claim 1, wherein the trace width of the second interconnection scheme is larger than that of the first interconnection scheme.

14. The chip structure according to claim 1, wherein the trace width of the second interconnection scheme ranges from 1 micron to 1 centimeter.

15. The chip structure according to claim 1, wherein the cross-sectional area of the traces of the second interconnection scheme is larger than that of the traces of the first interconnection scheme.

16. The chip structure according to claim 1, wherein the cross-sectional area of the traces of the second interconnection scheme ranges from 1 square micron to 0.5 square millimeters.

17. The chip structure according to claim 1, wherein the second interconnection scheme includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler ranges from 1 square micron to 10,000 square microns.

18. A chip structure, comprising:

a substrate having a plurality of electric devices that are disposed on a surface of the substrate;

a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and an interconnection scheme, the interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the interconnection scheme electrically connected to the electric devices;

a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the interconnection scheme; and

a second built-up layer arranged over the passivation layer, the second built-up layer provided with at least one power bus, the power bus electrically connected to the interconnection layer with passing through the opening of the passivation layer.

19. The chip structure according to claim 18, wherein the trace thickness of the power bus ranges from 1 micron to 50 microns.

20. The chip structure according to claim 18, wherein the trace width of the power bus ranges from 1 micron to 1 centimeter.

21. The chip structure according to claim 18, wherein the cross-sectional area of the traces of the power bus ranges from 1 square micron to 0.5 square millimeters.

22. The chip structure according to claim 18, wherein the passivation layer is constructed of an inorganic compound.

23. The chip structure according to claim 18, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.

24. The chip structure according to claim 18, wherein the second built-up layer further includes a dielectric body and the power bus interlaces inside the dielectric body of the second built-up layer.

25. The chip structure according to claim 24, wherein the dielectric body of the second built-up layer is made of an organic compound.

26. The chip structure according to claim 24, wherein the dielectric body of the second built-up layer is made of a macromolecule polymer.

27. The chip structure according to claim 24, wherein the dielectric body of the second built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

28. The chip structure according to claim 24, wherein the dielectric body of the second built-up layer is composed of at least one dielectric layer, and the thickness of the dielectric layer ranges from 1 micron to 100 microns.

29. The chip structure according to claim 24, wherein the dielectric body of the first built-up layer is composed of at least one first dielectric layer, the dielectric body of the second built-up layer is composed of at least one second dielectric layer, and the second dielectric layer is thicker than the first dielectric layer.

30. The chip structure according to claim 24, wherein the power bus includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler ranges from 1 square micron to 10,000 square microns.

31. The chip structure according to claim 18, wherein the power bus includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler is larger than that of the opening of the passivation layer.

32. The chip structure according to claim 18, wherein the power bus is of a planar type.

33. The chip structure according to claim 18, wherein at least one of the electric devices is an electrostatic discharge circuit, and the electrostatic discharge circuit is electrically connected with the interconnection scheme.

34. The chip structure according to claim 18, wherein the interconnection scheme includes at least one first conductive pad and at least one second conductive pad, the openings of the passivation layer expose the first conductive pad and the second conductive pad, the second conductive pad is electrically connected with the power bus, and the first conductive pad is exposed to the outside.

35. The chip structure according to claim 34, wherein the interconnection scheme further includes at least one linking trace, through which the first conductive pad is electrically connected with the second conductive pad.

36. The chip structure according to claim 35, wherein the linking trace is shorter than 5,000 microns.

37. The chip structure according to claim 18, wherein the trace thickness of the power bus is larger than that of the interconnection scheme.

38. The chip structure according to claim 18, wherein the trace width of the power bus is larger than that of the interconnection scheme.

39. The chip structure according to claim 18, wherein the cross-sectional area of the traces of the power bus is larger than that of the traces of the interconnection scheme.

40. The chip structure according to claim 18, wherein the largest width of the opening of the passivation layer ranges from 0.5 microns to 200 microns.

41. A chip structure, comprising:

a substrate having a plurality of electric devices that are disposed on a surface of the substrate;

a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and an interconnection scheme, the interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the interconnection scheme electrically connected to the electric devices;

a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the interconnection scheme; and

a second built-up layer arranged over the passivation layer, the second built-up layer provided with at least one ground bus, the ground bus electrically connected to the interconnection layer with passing through the opening of the passivation layer.

42. The chip structure according to claim 41, wherein the trace thickness of the ground bus ranges from 1 micron to 50 microns.

43. The chip structure according to claim 41, wherein the trace width of the ground bus ranges from 1 micron to 1 centimeter.

44. The chip structure according to claim 41, wherein the cross-sectional area of the traces of the ground bus ranges from 1 square micron to 0.5 square millimeters.

45. The chip structure according to claim 41, wherein the passivation layer is constructed of an inorganic compound.

46. The chip structure according to claim 41, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.

47. The chip structure according to claim 41, wherein the second built-up layer further includes a dielectric body and the ground bus interlaces inside the dielectric body of the second built-up layer.

48. The chip structure according to claim 47, wherein the dielectric body of the second built-up layer is made of an organic compound.

49. The chip structure according to claim 47, wherein the dielectric body of the second built-up layer is made of a macromolecule polymer.

50. The chip structure according to claim 47, wherein the dielectric body of the second built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

51. The chip structure according to claim 47, wherein the dielectric body of the second built-up layer is composed of at least one dielectric layer, and the thickness of the dielectric layer ranges from 1 micron to 100 microns.

52. The chip structure according to claim 47, wherein the dielectric body of the first built-up layer is composed of at least one first dielectric layer, the dielectric body of the second built-up layer is composed of at least one second dielectric layer, and the second dielectric layer is thicker than the first dielectric layer.

53. The chip structure according to claim 41, wherein the ground bus includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler ranges from 1 square micron to 10,000 square microns.

54. The chip structure according to claim 41, wherein the ground bus includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler is larger than that of the opening of the passivation layer.

55. The chip structure according to claim 41, wherein the ground bus is of a planar type.

56. The chip structure according to claim 41, wherein at least one of the electric devices is an electrostatic discharge circuit, and the electrostatic discharge circuit is electrically connected with the interconnection scheme.

57. The chip structure according to claim 41, wherein the interconnection scheme includes at least one first conductive pad and at least one second conductive pad, the openings of the passivation layer expose the first conductive pad and the second conductive pad, the second conductive pad is electrically connected with the ground bus, and the first conductive pad is exposed to the outside.

58. The chip structure according to claim 57, wherein the interconnection scheme further includes at least one linking trace, through which the first conductive pad is electrically connected with the second conductive pad.

59. The chip structure according to claim 58, wherein the linking trace is shorter than 5,000 microns.

60. The chip structure according to claim 41, wherein the trace thickness of the ground bus is larger than that of the interconnection scheme.

61. The chip structure according to claim 41, wherein the trace width of the ground bus is larger than that of the interconnection scheme.

62. The chip structure according to claim 41, wherein the cross-sectional area of the traces of the ground bus is larger than that of the traces of the interconnection scheme.

63. The chip structure according to claim 41, wherein the largest width of the opening of the passivation layer ranges from 0.5 microns to 200 microns.

64. A chip structure, comprising:

a substrate having a plurality of electric devices that are disposed on a surface of the substrate;

a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the dielectric body of the first built-up layer and is electrically connected to the electric devices;

a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the first interconnection scheme; and

a second built-up layer arranged over the passivation layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected to the first interconnection layer with passing through the opening of the passivation layer, wherein a signal is transmitted from one of the electric devices to the first interconnection scheme, then passes through the passivation layer, and finally is transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme with passing through the passivation layer, and finally is transmitted to the other one or more of the electric devices.

65. The chip structure according to claim 64, wherein the passivation layer is constructed of an inorganic compound.

66. The chip structure according to claim 64, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.

67. The chip structure according to claim 64, wherein the second built-up layer further includes a dielectric body and the second interconnection scheme interlaces inside the dielectric body of the second built-up layer.

68. The chip structure according to claim 67, wherein the dielectric body of the second built-up layer is made of an organic compound.

69. The chip structure according to claim 67, wherein the dielectric body of the second built-up layer is made of a macromolecule polymer.

70. The chip structure according to claim 67, wherein the dielectric body of the second built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

71. The chip structure according to claim 64, wherein at least one of the electric devices is a transition device, the transition device is electrically connected with the first interconnection scheme, a signal is transmitted from the transition device to the first interconnection scheme, then passes through the passivation layer, and finally is transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme with passing through the passivation layer, and finally is transmitted to the other one or more of the electric devices.

72. The chip structure according to claim 71, wherein the transition device is a driver, a receiver or an I/O circuit.

73. The chip structure according to claim 64, wherein the first interconnection scheme includes at least one first conductive pad and at least one second conductive pad, the openings of the passivation layer expose the first conductive pad and the second conductive pad, the second conductive pad is electrically connected with the second interconnection scheme, and the first conductive pad is exposed to the outside.

74. The chip structure according to claim 73, wherein the first interconnection scheme further includes at least one linking trace, through which the first conductive pad is electrically connected with the second conductive pad.

75. The chip structure according to claim 74, wherein the linking trace is shorter than 5,000 microns.

76. A chip, comprising an interconnection scheme and a passivation layer, the interconnection scheme arranged inside the chip, the passivation layer disposed on a surface layer of the chip, the passivation layer having at least one opening exposing the interconnection scheme, and the largest width of the opening of the passivation layer ranging from 0.5 microns to 20 microns.

77. A chip structure, comprising:

a chip having a first interconnection scheme and a passivation layer, the first interconnection scheme arranged inside the chip, the passivation layer disposed on a surface layer of the chip, the passivation layer having at least one opening exposing the first interconnection scheme, and the largest width of the opening of the passivation layer ranging from 0.5 microns to 20 microns; and

an built-up layer disposed on the passivation layer of the chip, the built-up layer having a second interconnection scheme, and the second interconnection scheme electrically connected to the first interconnection scheme with passing through the opening of the passivation layer.

78. The chip structure according to claim 77, wherein the trace thickness of the second interconnection scheme ranges from 1 micron to 50 microns.

79. The chip structure according to claim 77, wherein the trace width of the second interconnection scheme ranges from 1 micron to 1 centimeter.

80. The chip structure according to claim 77, wherein the cross-sectional area of the traces of the second interconnection scheme ranges from 1 square micron to 0.5 square millimeters.

81. The chip structure according to claim 77, wherein the passivation layer is constructed of an inorganic compound.

82. The chip structure according to claim 77, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.

83. The chip structure according to claim 77, wherein the built-up layer further includes a dielectric body and the second interconnection scheme interlaces inside the dielectric body of the built-up layer.

84. The chip structure according to claim 83, wherein the dielectric body of the built-up layer is made of an organic compound.

85. The chip structure according to claim 83, wherein the dielectric body of the built-up layer is made of a macromolecule polymer.

86. The chip structure according to claim 83, wherein the dielectric body of the built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

87. The chip structure according to claim 83, wherein the dielectric body of the built-up layer is composed of at least one dielectric layer, and the thickness of the dielectric layer ranges from 1 micron to 100 microns.

88. The chip structure according to claim 77, wherein the ground bus includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, the via metal filler is electrically connected with the first dielectric layer with passing through the opening of the passivation layer, and the cross-sectional area of the via metal filler is larger than that of the opening of the passivation layer.

89. The chip structure according to claim 77, wherein the second interconnection scheme includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler ranges from 1 square micron to 10,000 square microns.

90. A chip structure, comprising:

a substrate having a plurality of electric devices that are disposed on a surface of the substrate;

a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, the first interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the first interconnection scheme electrically connected to the electric devices, the first interconnection scheme including at least one first conductive pad and at least one second conductive pad, and both the first conductive pad and the second conductive pad located on a surface of the first built-up layer;

a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the first conductive pad and the second conductive pad, and the first conductive pad exposed to the outside; and

a second built-up layer deposited on the passivation layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected with the first interconnection layer through the second conductive pad.

91. The chip structure according to claim 90, wherein the second built-up layer further includes a dielectric body and the second interconnection scheme interlaces inside the dielectric body of the second built-up layer.

92. The chip structure according to claim 91, wherein the dielectric body of the second built-up layer is made of an organic compound.

93. The chip structure according to claim 91, wherein the dielectric body of the second built-up layer is made of a macromolecule polymer.

94. The chip structure according to claim 91, wherein the dielectric body of the second built-up layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

95. The chip structure according to claim 90, wherein at least one of the electric devices is an electrostatic discharge circuit and the electrostatic discharge circuit is electrically connected with the first interconnection scheme.

96. The chip structure according to claim 90, wherein at least one of the electric devices is a transition device, the transition device is electrically connected with the first interconnection scheme, a signal is transmitted from the transition device to the first interconnection scheme and then transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme and finally transmitted to the other one or more of the electric devices.

97. The chip structure according to claim 96, wherein the transition device is a driver, a receiver or an I/O circuit.

98. The chip structure according to claim 90, wherein the first interconnection scheme further includes at least one linking trace, through which the first conductive pad is electrically connected with the second conductive pad.

99. The chip structure according to claim 98, wherein the linking trace is shorter than 5,000 microns.

100. The chip structure according to claim 90, wherein the trace thickness of the second interconnection scheme is larger than that of the first interconnection scheme.

101. The chip structure according to claim 90, wherein the trace thickness of the second interconnection scheme ranges from 1 micron to 50 microns.

102. The chip structure according to claim 90, wherein the trace width of the second interconnection scheme is larger than that of the first interconnection scheme.

103. The chip structure according to claim 90, wherein the trace width of the second interconnection scheme ranges from 1 micron to 1 centimeter.

104. The chip structure according to claim 90, wherein the cross-sectional area of the traces of the second interconnection scheme is larger than that of the traces of the first interconnection scheme.

105. The chip structure according to claim 90, wherein the cross-sectional area of the traces of the second interconnection scheme ranges from 1 square micron to 0.5 square millimeters.

106. The chip structure according to claim 90, wherein the second interconnection scheme includes at least one metal layer and at least one via metal filler, the metal layer is electrically connected with the via metal filler, and the cross-sectional area of the via metal filler ranges from 1 square micron to 10,000 square microns.

107. The chip structure according to claim 90, wherein the largest width of the opening of the passivation layer ranges from 0.5 microns to 200 microns.

108. The chip structure according to claim 90, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.