Method for testing semiconductor wafers

• US 6,798,224 B1
• Filed: 02/05/2002
• Issued: 09/28/2004
• Est. Priority Date: 02/11/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Krivy, Andrew J., Farnworth, Warren M., Hembree, David R., Wood, Alan G., Akram, Salman, Doherty, C. Patrick
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/072,734
• Time in Patent Office: 966 Days
• Field of Search: 324/754, 324/755, 324/575, 324/578, 324/761, 324/765, 439/66, 439/67, 439/68, 439/71, 439/73
• US Class Current: 324/754.12
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

Claims

1. A method for testing a semiconductor wafer comprising:

providing a testing apparatus comprising a test circuitry configured to apply test signals to the wafer, a suspended plate, a substrate on the suspended plate, and a force applying mechanism comprising a plurality of electrical connectors in contact with the suspended plate in electrical communication with the test circuitry;

biasing the substrate against the wafer using the suspended plate and the force applying mechanism; and

applying the test signals through the electrical connectors, through the suspended plate and through the substrate to the wafer.

2. The method of claim 1 wherein a membrane mounts the suspended plate on the testing apparatus.

3. The method of claim 1 further comprising providing a compressible member between the suspended plate and the substrate.

4. The method of claim 1 wherein the substrate includes a plurality of contact members configured to electrically contact a plurality of contact locations on the wafer.

5. The method of claim 4 wherein each contact member comprises an indentation in the substrate or a projection on the substrate.

6. The method of claim 1 wherein the testing apparatus comprises a wafer prober.

7. In a test system including a testing apparatus for a semiconductor wafer, a method for testing the wafer comprising:

suspending a substrate on the testing apparatus;

providing a force applying mechanism on the testing apparatus comprising a plurality of electrical connectors configured to bias the substrate against the wafer;

biasing the substrate against the wafer using the force applying mechanism; and

applying test signals through the electrical connectors and the substrate to the wafer.

8. The method of claim 7 wherein the suspending step is performed by connecting a membrane to a plate attached to the substrate.

9. The method of claim 8 wherein each electrical connector comprises a pin.

10. The method of claim 9 wherein the substrate comprises a plurality of contact members configured to electrically engage contact locations on the wafer.

11. The method of claim 10 wherein the contact locations comprise bumps and the contact members comprise indentations and conductive layers on the indentations.

12. The method of claim 10 wherein the contact locations comprise pads and the contact members comprise projections configured to penetrate the pads.