Tester channel to multiple IC terminals

• US 6,798,225 B2
• Filed: 05/08/2002
• Issued: 09/28/2004
• Est. Priority Date: 05/08/2002
• Status: Expired due to Term

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/142,550
• Publication Number:
  US 20030210031A1
• Time in Patent Office: 874 Days
• Field of Search: 324/754, 324/757-758, 324/760, 324/762, 324/765, 324/158.1, 714/724, 714/734, 714/738, 714/742, 333/33, 333/246-247, 702/85-89, 702/104-119
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: Y10T 29/49082 Resistor making
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads. The tester channel measures the voltage of its input signal so that the logic state of the signals produced at each of the N IC output pads can be determined from the measured voltage.

Claims

1. An apparatus for providing signal paths between integrated circuit (IC) tester channels and input and output pads residing on surfaces of a plurality of ICs, wherein the ICs are adapted to receive test signals via the input pads and to generate output signals at the output pads in response to the test signals, and wherein voltages of the test signals and the output signals represent logic states, the apparatus comprising:

a first node; and

N first signal paths,

wherein N is an integer greater than one,

wherein each first signal path links a separate one of the output pads to the first node, such that a first signal is produced at the first node in response to a set of N output signals generated at the output pads linked to the first node, and

wherein all N first signal paths have substantially differing resistances such that a voltage of the first signal has a unique magnitude for each unique combination of logic states of the set of N output signals.

2. The apparatus in accordance with claim 1 further comprising first conductive means for delivering the first signal appearing at the first node as an input signal to one of the IC tester channels.

3. The apparatus in accordance with claim 1 further comprising:

a second circuit node;

a plurality of second signal paths, each corresponding to a separate one of the IC input pads and delivering a test signal from the second circuit node to the corresponding IC input pad, wherein each second signal path is of sufficient resistance that a short linking the corresponding IC input pad to any source of potential within the IC upon which the IC input pad resides would not alter the logic state of the test signal at the second circuit node.

4. The apparatus in accordance with claim 3 further comprising:

first conductive means for delivering the first signal appearing at the first node as an input signal to one of the IC tester channels, and

second conductive means for delivering a test signal produced by another of said tester channels to the second circuit node.

5. An apparatus for providing signal paths between integrated circuit (IC) tester channels and input pads and output pads residing on surfaces of a plurality of ICs, wherein the ICs are adapted to receive test signals via the input pads and to generate output signals at the output pads in response to the test signals, and wherein voltages of the test signals and the output signals represent logic states, the apparatus comprising:

at least one substrate having a surface;

a first circuit node formed on said at least one substrate;

N first conductive pads formed on said surface, where N is an integer greater than 1;

N first probes, each first probe linking a separate one of N of said output pads to a corresponding one of the N first conductive pads; and

N first signal paths, each linking a corresponding one of the N first conductive pads to said first circuit node such that a first signal is produced at the first circuit node in response to a set of N output signals generated at the output pads linked to the first circuit node, all N first signal paths have substantially differing resistances such that a voltage of the first signal has a unique magnitude for each unique combination of logic states of the set of N output signals.

6. The apparatus in accordance with claim 5 wherein portions of the N first signal paths are formed on said at least one substrate.

7. The apparatus in accordance with claim 5 wherein said at least one substrate comprises:

a first substrate having said surface; and

a second substrate, spaced from said first substrate, said first circuit node being formed on said second substrate, wherein said first signal paths are formed on and extend between the first and second substrates.

8. The apparatus in accordance with claim 5 where said at least one substrate comprises:

a first substrate having said surface; and

a second substrate, spaced from said first substrate, said first circuit node being formed on said second substrate; and

a third substrate residing between and spaced from said first and second substrates, wherein said first signal paths are formed on and extend between the first, second and third substrates.

9. The apparatus in accordance with claim 5 further comprising first conductive means for delivering the first signal appearing at the first circuit node as an input signal to one of the IC tester channels.

10. The apparatus in accordance with claim 5 wherein each first probe comprises a spring contact.

11. The apparatus in accordance with claim 5 wherein the apparatus further comprises:

a second circuit node formed on the substrate;

a plurality of second conductive pads formed on the surface of the substrate;

a plurality of second probes, each second probe linking a separate one said input pads to a corresponding one of the plurality of second conductive pads; and

a plurality of second signal paths, each corresponding to a separate one of the second conductive pads for delivering a test signal applied to the second circuit node to the corresponding second conductive contact, wherein each second signal path has substantial resistance sufficient to prevent a fault at any of the inputs pads from affecting a logic state of the test signal applied at the second circuit node.

12. The apparatus in accordance with claim 11 further comprising:

first conductive means for delivering the first signal appearing at the first circuit node as an input signal to one of the IC tester channels, and

second conductive means for delivering a test signal produced by another of said tester channels to the second circuit node.

13. The apparatus in accordance with claim 12 wherein each first probe and each second probe comprises a spring contact.

14. An apparatus for testing integrated circuit (ICs), wherein the ICs have input pads at which the ICs receive test signals, and have output pads at which they produce output signals in response to the test signals, the test and output signals having voltages representing logic states, the apparatus comprising:

a first circuit node;

N first signal paths, wherein N is an integer greater than one, wherein each first signal path links a separate one of the output pads to the first circuit node, and wherein each first signal path has a resistance differing substantially from a resistance of any other of the first signal paths, such that a first signal appears at the first circuit node having a first voltage representing a combination of logic states of the output signals produced by the output pads linked by the first signal paths to the first circuit node; and

a first IC tester channel linked to the first circuit node including means for measuring the first voltage of the first signal.

15. The apparatus in accordance with claim 14 wherein the means for measuring the first voltage of the first signal comprises an analog-to-digital converter (ADC) for generating output data in response to the first signal, wherein a value of the output data represents a voltage range in which said first voltage resides.

16. The apparatus in accordance with claim 15 wherein the ADC comprises:

a digital-to-analog converter (DAC) for generating a reference voltage of magnitude determined by a value of control data supplied as input to the DAC; and

a comparator receiving the reference voltage and the first signal for generating an output bit indicating whether the first voltage is greater than the reference voltage.

17. The apparatus in accordance with claim 16 wherein the ADC further comprises means for periodically altering the value of the control data.

18. The apparatus in accordance with claim 15 wherein the ADC comprises:

means for generating M reference voltages, of substantially differing magnitudes, where M is an integer greater than 1, and

M comparators, each comparator corresponding to a separate one of the M reference voltages, each comparator receiving its corresponding reference voltage and the first signal as inputs, and each comparator generating a separate bit of an M-bit data word, wherein the bit generated by each comparator indicates whether the first voltage is greater than its corresponding reference voltage.

19. The apparatus in accordance with claim 18 wherein M is at least as large as 2^N−

1 and wherein the magnitudes of said M reference voltages are such that each possible combination of logic states of the output signals produced by the output pads linked by the first signal paths to the first circuit node results in a unique value of the M-bit data word.

20. A method for testing at least one integrated circuit (IC) device wherein at least one IC device comprises a plurality of terminals at which said at least one IC device receives input signals and concurrently produces output signals, wherein voltages of the input and output signals represent logic states, the method comprising the steps of:

a. providing a first circuit node;

b. providing a plurality of first signal paths, each first signal path linking a separate one of the plurality of terminals to the first circuit node, such that a first signal is produced at the first circuit node in response to IC output signals concurrently generated at each of the plurality of IC terminals, wherein all first signal paths have substantially differing resistances such that a voltage of the first signal produced at the first circuit node has a unique magnitude for each unique combination of logic states of the IC output signals produced at the plurality of IC terminals;

c. measuring a voltage of the first signal produced at the first circuit node; and

d. determining a logic state of each of the plurality of output signals from the voltage measured at step c.

21. The method in accordance with claim 20 further comprising the step of:

e. applying a test signal to the first circuit node such that the test signal travels from the first circuit node to each of the plurality of IC terminals via a separate one of the first signal paths, such that the test signal becomes an input signal received by each of the plurality of IC terminals.