Logic circuitry with shared lookup table

• US 6,798,240 B1
• Filed: 01/24/2003
• Issued: 09/28/2004
• Est. Priority Date: 01/24/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh V
• Application Number:
  US10/351,026
• Time in Patent Office: 613 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/41, 326/47, 326/49, 326/101
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A particular embodiment of the present invention provides a shared-LUT logic circuit that provides the functionality of two (n+1)LUT logic circuits without requiring approximately twice the sources of two nLUT circuits. In some embodiments, a shared-LUT logic circuit is provided that can be configured to operate in multiple modes including, for example, an nLUT mode, an (n+1)LUT mode, and other modes.

Claims

1. A logic circuit comprising:

first n-input LUT circuitry;

second n-input LUT circuitry; and

a plurality of muxes interposed between an x and an x+1 mux level of the first and second n-input LUT circuitry, each mux of the plurality of interposed muxes including;

a first input coupled to an output of an x+1 level mux of the first n-input LUT circuitry;

a second input coupled to an output of an x+1 level mux of the second n-input LUT circuitry; and

an output coupled to an input of an x level mux of the first or second n-input LUT circuitry.

2. The logic circuit of claim 1 wherein:

the logic circuit provides first and second n+1-input LUT circuits;

control inputs of the plurality of interposed muxes are coupled to an n+1'"'"'th logic input the first n+1-input LUT circuit or to an n+1'"'"'th logic input of the second n+1-input LUT circuit; and

at least one input of the first n+1-input LUT circuit is coupled to receive the same signal as at least one input of the second n+1-input LUT circuit.

3. The logic circuit of claim 2 further comprising:

a first additional mux including a first input coupled to receive a first input signal, a second input coupled to receive a second input signal, and an output coupled to provide either the first or second input signal to an input of the first n+1-input LUT circuit;

a second additional mux including a first input coupled to receive a first input signal, a second input coupled to receive a second input signal, and an output coupled to provide either the first or second input signal received by the second additional mux to an input of the second n+1-input LUT circuit;

a first tie-off mux including a first input coupled to receive an input signal, a second input coupled to receive a first tie-off value, and an output coupled to provide either the input signal or the first tie-off value to muxes of the plurality of interposed muxes; and

a second tie-off mux including a first input coupled to receive an input signal, a second input coupled to receive a second tie-off value, and an output coupled to provide either the input signal or the second tie-off value to muxes of the plurality of interposed muxes.

4. The logic circuit of claim 3 wherein:

the first additional mux, the second additional mux, the first tie-off mux, and the second tie-off mux are configurable so that the logic circuit can provide either two n-input LUT circuits having independently programmable functions or two n+1-input LUT circuits having the same programmable functions.

5. The logic circuit of claim 3 wherein at least one of the first and second tie-off values is dynamic.

6. The logic circuit of claim 3 wherein at least one of the first and second tie-off values is fixed.

7. The logic circuit of claim 3 wherein the first tie-off value is low and the second tie-off value is high.

8. The logic circuit of claim 3 wherein the first input of the first tie-off mux is coupled to receive the same input signal as one of the inputs of the first additional mux and the first input of the second tie-off mux is coupled to receive the same input signal as one of the inputs of the second additional mux.

9. The logic circuit of claim 3 further comprising:

a third additional mux including a first input coupled to a memory element providing a set value, a second input coupled to receive the same input signal received by the first input of the first tie-off mux, and an output coupled to control inputs of muxes of the plurality of muxes; and

a fourth additional mux including an inverting input coupled to the memory element to receive the set value and provide an inverted set value to the fourth additional mux, the fourth additional mux also including another input coupled to receive the same signal as the first input of the second tie-off mux and an output coupled to control inputs of muxes of the plurality of muxes.

10. The logic circuit of claim 9 wherein:

the first additional mux, the second additional mux, the third additional mux, the fourth additional mux, the memory element, the second tie-off mux, and the first tie-off mux are configurable so that the logic circuit can provide either two n-input LUT circuits having independently programmable functions, two n+1-input LUT circuits having the same programmable functions, or two n+2-input LUT circuits having incomplete programmable functions.

11. The logic circuit of claim 1 wherein the value of n is even and the value of x is such that 2x=n.

12. The logic circuit of claim 1 wherein the value of n is odd and the value of x is such that either 2x+1 or 2x−

1 is equal to n.

13. The logic circuit of claim 2 wherein:

the plurality of interposed muxes includes a first plurality of interposed muxes and a second plurality of interposed muxes;

outputs of the first plurality of interposed muxes being coupled an input of an x level mux of the first n-input LUT circuitry and control inputs of the first plurality of interposed muxes being coupled to the n+1'"'"'th input of the first n+1-input LUT circuit; and

outputs of the second plurality of interposed muxes being coupled to an input of an x level mux of the n-input LUT circuitry and control inputs of the second plurality of interposed muxes being coupled to the n+1'"'"'th input of the second n+1-input LUT circuit.

14. A programmable logic device comprising the logic circuit of claim 1.

15. A data processing system comprising the programmable logic device of claim 14.

16. A programmable logic device comprising the logic circuit of claim 3.

17. A data processing system comprising the programmable logic device of claim 16.

18. A programmable logic device comprising the logic circuit of claim 9.

19. A data processing system comprising the programmable logic device of claim 18.

20. A logic circuit comprising:

first n-input LUT circuitry;

second n-input LUT circuitry; and

a plurality of muxes interposed between a last mux level and memory elements of the first and second n-input LUT circuitry, each mux of the plurality of interposed muxes including;

a first input coupled to a memory element of the first n-input LUT circuitry;

a second input coupled to a memory element of the second n-input LUT circuitry; and

an output coupled to an input of a last-level mux of the first or second n-input LUT circuitry.

21. The logic circuit claim 20 wherein the logic circuit provides first and second n+1-input LUT circuits, control inputs of the plurality of interposed muxes being coupled to an n+1'"'"'th logic input the first n+1-input LUT circuit or to an n+1'"'"'th logic input of the second n+1-input LUT circuit.

22. The logic circuit of claim 21 wherein:

the plurality of interposed muxes includes a first plurality of interposed muxes and a second plurality of interposed muxes;

outputs of the first plurality of interposed muxes being coupled to an input of a last-level mux of the first n-input LUT circuitry and control inputs of the first plurality of interposed muxes being coupled to the n+1'"'"'th input of the first n+1-input LUT circuit; and

outputs of the second plurality of interposed muxes being coupled to an input of a last-level mux of the second n-input LUT circuitry and control inputs of the second plurality of interposed muxes being coupled to the n+1'"'"'th input of the second n+1-input LUT circuit.

23. A programmable logic device comprising the logic circuit of claim 20.

24. A data processing system comprising the programmable logic device of claim 23.

25. A logic circuit comprising:

first n-input LUT means;

second n-input LUT means; and

a plurality of selection means interposed between selection levels of the first and second n-input LUT means, the plurality of selection means coupling the first n-input LUT means with the second n-input LUT means such that the logic circuit provides two n+1-input LUT means for implementing two related n+1-input logic functions.

26. The logic circuit of claim 25 further comprising:

a plurality of selection means coupled to inputs of the logic circuit for implementing and providing selection such that the logic circuit provides either two n+1-input LUT means for implementing two n-input logic functions that are the same or two n-input LUT means for implementing two independent n-input logic functions.

27. The logic circuit of claim 26 further comprising:

an additional plurality of selection means coupled to the logic circuit for implementing and providing further such that the logic circuit may also provide two n+2-input LUT means for implementing two incomplete and related n+2-input functions.

28. A programmable logic device comprising the logic circuit of claim 25.

29. A data processing system comprising the programmable logic device of claim 28.

30. A programmable logic device comprising the logic circuit of claim 26.

31. A data processing system comprising the programmable logic device of claim 30.

32. A programmable logic device comprising the logic circuit of claim 27.

33. A data processing system comprising the programmable logic device of claim 32.

34. A look-up table (LUT) based logic element (LE), comprising:

m data inputs;

two data outputs;

2k bits of LUT mask,

wherein

the LE includes first and second circuitry configured to accomplish first and second respective identical Boolean functions, each of the first and second circuitry operating on k data inputs responsive to a separate 2k−

1 bits of the 2k bits of LUT mask, wherein 2k−

m inputs of the m inputs are shared between the first and second circuitry and m−

k inputs of each k inputs are independent inputs.

35. The LE of claim 34, wherein:

m=k+2;

each of the first and second circuitry includes base circuitry comprising a plurality of multiplexor stages to nominally accomplish a k−

1 LUT function operating responsive to the separate 2k−

1 bits of the 2k bits of LUT mask;

each of the first and second circuitry further includes an additional stage inserted between a first, earlier, multiplexor stage and a second, later, multiplexor stage of the base circuitry, the additional stage of each of the first and second circuitry configured to selectively pass the outputs from the earlier stage of that circuitry or from the earlier stage of the other circuitry, to the later stage of that circuitry,

the first and second circuitry thereby collectively forming two k input LUT functions with no additional LUT mask bits beyond the 2k bits of LUT mask.