Method and apparatus for characterizing switching history impact

• US 6,798,261 B1
• Filed: 05/22/2003
• Issued: 09/28/2004
• Est. Priority Date: 05/22/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ketchen, Mark B., Bhushan, Manjul, Pearson, Dale J.
• Primary Examiner(s): Nguyen, Linh M.
• Application Number:
  US10/443,515
• Time in Patent Office: 495 Days
• Field of Search: 327/172, 327/173, 327/174, 327/175, 327/176, 327/31, 327/35
• US Class Current: 327/172
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence

Abstract

A method for characterizing a change in delay induced by a switching history of a circuit includes the steps of generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal; varying the pulse width of the first signal; monitoring the second signal; determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.

Claims

1. Apparatus for characterizing a change in delay induced by a switching history of a circuit, the apparatus comprising:

a pulse generator configurable for generating a signal having a pulse width that is selectively adjustable, the signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another;

a first delay circuit coupled to the pulse generator, the first delay circuit being configurable for receiving the signal from the pulse generator and generating an output signal at an output of the first delay circuit, the first delay circuit having a first switch delay characteristic of the first edge of the received signal and a second switch delay characteristic of the second edge of the received signal, wherein the pulse width of the signal generated by the pulse generator is less than the first switch delay associated with the first delay circuit; and

a controller, operative to;

(i) vary the pulse width of the signal generated by the pulse generator;

(ii) monitor the output signal;

(iii) determine a value of the pulse width that defines a boundary of when the output signal is present and when the output signal is not present; and

(iv) determine a ratio of the value of the pulse width that defines the boundary to at least one of the first switch delay and the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.

2. The apparatus of claim 1, wherein the pulse generator comprises an edge sharpener circuit configurable for receiving an input edge and generating the first edge of the signal, the input edge having a rate of change of amplitude associated therewith that is substantially slower than a rate of change of amplitude associated with the first edge of the signal.

3. The apparatus of claim 2, wherein the input edge received by the edge sharpener circuit is generated by a substantially direct current (DC) signal.

4. The apparatus of claim 1, wherein the pulse generator comprises a second delay circuit including a plurality of delay elements connected in a series chain, at least a portion of the delay elements being scaled to at least one of the first switch delay and the second switch delay associated with the first delay circuit, the second delay circuit including a plurality of feedback paths for operatively adjusting the pulse width of the signal.

5. The apparatus of claim 4, wherein a delay of the second edge relative to the first edge is operatively adjusted by selecting one of the plurality of feedback paths associated with the second delay circuit, the pulse width of the signal being proportional to the delay of the second edge relative to the first edge.

6. The apparatus of claim 4, wherein the second delay circuit comprises a tapped delay chain including a plurality of output taps, the pulse width of the signal being adjusted by operatively selecting one of the output taps.

7. The apparatus of claim 6, wherein the output taps are selected sequentially.

8. The apparatus of claim 6, wherein the output taps are selected using a successive approximation algorithm.

9. The apparatus of claim 4, wherein the first and second edges are operatively summed together at an output of the pulse generator to form the signal received by the first delay circuit.

10. The apparatus of claim 1, wherein the first delay circuit comprises at least a portion of the pulse generator.

11. The apparatus of claim 1, wherein the pulse generator is configurable for adjusting the pulse width of the signal in predetermined steps, the size of each of the steps being scaled to at least one of the first switch delay and the second switch delay associated with the first delay circuit.

12. The apparatus of claim 1, wherein the first delay circuit comprises a plurality of delay elements connected in a series chain.

13. The apparatus of claim 1, wherein the first delay circuit comprises the pulse generator.

14. The apparatus of claim 1, wherein the circuit to be characterized comprises at least one silicon-on-insulator circuit.

15. The apparatus of claim 1, further comprising a pulse detector coupled to the output of the first delay circuit, the pulse detector being configurable for monitoring the output signal from the first delay circuit and providing an indication of at least one of when the output signal is present at the output of the first delay circuit and when the output signal is not present at the output of the first delay circuit.

16. The apparatus of claim 15, wherein the pulse detector is configurable to at least temporarily store the indication of when the output signal is present at the output of the first delay circuit.

17. The apparatus of claim 16, wherein the pulse detector comprises a latch circuit for storing the indication of when the output signal is present at the output of the first delay circuit.

18. The apparatus of claim 1, further comprising an offset adjust circuit operatively coupled to the output of the first delay circuit, the offset adjust circuit being configurable for modifying at least a pulse width of the output signal to be monitored by the controller by generating a delayed version of the output signal from the first delay circuit, the delayed version of the output signal having a first edge and a second edge associated therewith, the modified output signal having a first edge substantially matched to the first edge of the delayed version of the output signal and having a second edge substantially matched to the second edge of the output signal from the first delay circuit.

19. The apparatus of claim 18, wherein the offset adjust circuit comprises a second delay circuit for receiving the output signal from the first delay circuit and generating the delayed version of the output signal.

20. The apparatus of claim 19, wherein the offset adjust circuit further comprises a logical AND circuit including a first input for receiving the output signal from the first delay circuit, a second input for receiving the delayed version of the output signal from the second delay circuit, and an output for generating the modified output signal to be monitored by the controller.

21. The apparatus of claim 18, wherein the amount of delay associated with the delayed version of the output signal is scaled to the first switch delay associated with the first delay circuit.

22. The apparatus of claim 2, wherein the edge sharpener circuit comprises a latch circuit.

23. A semiconductor device including at least one apparatus for characterizing a change in delay induced by a switching history of a circuit, the at least one apparatus comprising:

a pulse generator configurable for generating a signal having a pulse width that is selectively adjustable, the signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another;

a first delay circuit coupled to the pulse generator, the first delay circuit being configurable for receiving the signal from the pulse generator and generating an output signal at an output of the first delay circuit, the first delay circuit having a first switch delay characteristic of the first edge of the received signal and a second switch delay characteristic of the second edge of the received signal, wherein the pulse width of the signal generated by the pulse generator is less than the first switch delay associated with the first delay circuit; and

a controller, operative to;

(i) vary the pulse width of the signal generated by the pulse generator;

(ii) monitor the output signal;

(iii) determine a value of the pulse width that defines a boundary of when the output signal is present and when the output signal is not present; and

(iv) determine a ratio of the value of the pulse width that defines the boundary to at least one of the first switch delay and the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.

24. The semiconductor device of claim 23, wherein the pulse generator in the at least one apparatus comprises a second delay circuit including a plurality of delay elements connected in a series chain, at least a portion of the delay elements being scaled to at least one of the first switch delay and the second switch delay associated with the first delay circuit, the second delay circuit including a plurality of feedback paths for operatively adjusting the pulse width of the signal.

25. The semiconductor device of claim 23, wherein the at least one apparatus further comprises a pulse detector coupled to the output of the first delay circuit, the pulse detector being configurable for monitoring the output signal from the first delay circuit and providing an indication of at least one of when the output signal is present at the output of the first delay circuit and when the output signal is not present at the output of the first delay circuit.

26. The semiconductor device of claim 23, wherein the at least one apparatus further comprises an offset adjust circuit operatively coupled to the output of the first delay circuit, the offset adjust circuit being configurable for modifying at least a pulse width of the output signal to be monitored by the controller by generating a delayed version of the output signal from the first delay circuit, the delayed version of the output signal having a first edge and a second edge associated therewith, the modified output signal having a first edge substantially matched to the first edge of the delayed version of the output signal and having a second edge substantially matched to the second edge of the output signal from the first delay circuit.

27. A method for characterizing a change in delay induced by a switching history of a circuit, the method comprising the steps of:

generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another;

generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal;

varying the pulse width of the first signal;

monitoring the second signal;

determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and

determining a ratio of the value of the pulse width that defines the boundary to at least one of the first switch delay and the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.