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Clamping circuit and method for DMOS drivers

  • US 6,798,271 B2
  • Filed: 04/04/2003
  • Issued: 09/28/2004
  • Est. Priority Date: 11/18/2002
  • Status: Active Grant
First Claim
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1. In an electrical circuit including an inductive load which has a first side driven by an FET pair including a high side transistor connected in series with a low side transistor between a supply voltage and a reference potential, wherein a second side of said inductive load is connected to a current carrying circuit capable of carrying current to a reference potential, and wherein said high side transistor has an associated body diode, a circuit comprising:

  • circuitry to operate said high side transistor and said current carrying circuit capable of carrying current to selectively allow a current to flow from said supply voltage through said high side transistor, said inductor, and said circuit capable of carrying current; and

    a transconductance circuit loop including a transconductance circuit connected to control said current carrying circuit capable of carrying current to pull current from said inductive load to said reference potential when said inductive load sources current to said body diode sufficient to cause the voltage across said body diode to exceed a predetermined trip voltage.

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