Graphics subsystem including a RAMDAC IC with digital video storage interface for connection to a graphics bus

• US 6,798,418 B1
• Filed: 05/24/2000
• Issued: 09/28/2004
• Est. Priority Date: 05/24/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sartori, Gabriele, Gulick, Dale E.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Singh, Dalip K.
• Application Number:
  US09/577,527
• Time in Patent Office: 1,588 Days
• Field of Search: 375/240, 375/240.27, 345/509, 345/643, 345/519, 345/506, 345/558, 345/420, 345/419, 345/501, 345/522, 345/520, 326/38, 710/26, 710/312, 710/305, 710/200, 710/56, 710/22, 710/52, 701/208, 711/147, 370/263
• US Class Current: 345/519
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/366 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit. The DMA controller is further configured to generate write cycles to cause digital RGB display data received from the color mapping unit, in the conversion unit, to be provided for storage in a specified region of memory. In another embodiment, the graphics subsystem may include a digital video interface implemented on the second integrated circuit chip. The digital video interface is configured to receive digital RGB display data from the color mapping unit and to provide an encoded digital video output to a digital video output port. The digital video interface is further configured to receive encoded digital video from a digital video input port and to provide decoded digital display data for storage on devices such as a digital VCR.

Claims

1. A graphics subsystem comprising:

a graphics processor implemented on a first integrated circuit chip, wherein said graphics processor is configured to render digital image information in response to a graphics command received from a CPU and to store said digital image information in a memory;

a conversion unit implemented on a second integrated circuit chip, wherein said conversion unit includes a color mapping unit coupled to convert said digital image information to digital RGB display data, wherein said conversion unit further includes a digital-to-analog converter coupled to convert said digital RGB display data to one or more analog signals for driving a video display; and

a DMA controller implemented on said second integrated circuit chip, wherein said DMA controller is configured to generate read requests to retrieve said digital image information stored in said memory and to cause said digital image information to be provided to said conversion unit;

wherein said DMA controller is further configured to generate write cycles to cause said digital RGB display data to be written to a designated memory region.

2. The graphics subsystem as recited in claim 1, wherein said color mapping unit includes a random access memory look-up table.

3. The graphics subsystem as recited in claim 1 further comprising:

a digital video interface implemented on said second integrated circuit chip, wherein said digital video interface is coupled to said conversion unit and to said DMA controller and is configured to receive said digital RGB display data and to provide an encoded digital video output.

4. The graphics subsystem as recited in claim 3, wherein said digital video interface is further configured to receive said encoded digital video and to provide decoded digital RGB display data.

5. The graphics subsystem as recited in claim 1 further comprising:

a display clock generator unit implemented on said second integrated circuit chip, wherein said display clock generator unit is coupled to said graphics processor and is configured to generate display timing signals for driving a video display.

6. The graphics subsystem as recited in claim 5 wherein said display timing signals include vertical and horizontal synchronization signals.

7. The graphics subsystem as recited in claim 6 further comprising:

a programmable timing control register unit implemented on said second integrated circuit chip, wherein said programmable timing control register unit is coupled to said display clock generator unit and is configured to store display timing information.

8. The graphics subsystem as recited in claim 7, wherein said programmable timing control register unit includes a plurality of registers.

9. The graphics subsystem as recited in claim 7, wherein said display timing information includes display resolution information and vertical and horizontal refresh information.

10. The graphics subsystem as recited in claim 9 further comprising:

a bus interface implemented on said second integrated circuit chip, wherein said bus interface is coupled to said graphics processor and is configured to receive packet-based information across a bus.

11. The graphics subsystem as recited in claim 10 further comprising:

a video stream interface implemented on said second integrated circuit chip, wherein said video stream interface configured to provide video image frame data for storage in a second memory.

12. The graphics subsystem as recited in claim 11 further comprising:

a graphics and video combiner unit implemented on said second integrated circuit chip, wherein said graphics and video combiner unit is coupled to said conversion unit and is configured to provide digital image information combined with video image frame data to said conversion unit.

13. The graphics subsystem as recited in claim 12 further comprising:

a frame synchronizer, wherein said frame synchronizer is coupled to said display clock generator unit and is configured to provide a video frame synchronization signal to said graphics and video combiner unit.

14. The graphics subsystem as recited in claim 13 further comprising:

a video stream timestamp processor, wherein said video stream timestamp processor is coupled to said frame synchronizer and is configured to provide a timestamp signal to said frame synchronizer.

15. The graphics subsystem as recited in claim 14 further comprising:

a video stream retriever, wherein said video stream retriever is coupled to said second memory and is configured to retrieve said video image frame data stored in said second memory and to cause said video image frame data to be provided to said graphics and video combiner unit.

16. The graphics subsystem as recited in claim 15 further comprising:

a video window resizing engine, wherein said video window resizing engine is coupled to said graphics and video combiner unit and is configured to mathematically resize said video image frame data dependent upon information stored in said programmable timing control register unit.

17. The graphics subsystem as recited in claim 11, wherein said second memory is a local frame store memory implemented on said second integrated circuit chip.

18. A computer system comprising:

a CPU;

a graphics subsystem coupled to said CPU including;

a graphics processor implemented on a first integrated circuit chip, wherein said graphics processor is configured to render digital image information in response to a graphics command received from said CPU and to store said digital image information in a first memory;

a conversion unit implemented on a second integrated circuit chip, wherein said conversion unit includes a color mapping unit coupled to convert said digital image information to digital RGB display data, wherein said conversion unit further includes a digital-to-analog converter coupled to convert said digital RGB display data to one or more analog signals for driving a video display; and

a DMA controller implemented on said second integrated circuit chip, wherein said DMA controller is configured to generate read requests to retrieve said digital image information stored in said first memory and to cause said digital image information to be provided to said conversion unit;

wherein said DMA controller is further configured to generate write cycles to cause said digital RGB display data to be written to a designated memory region.

19. The computer system as recited in claim 18, wherein said color mapping unit includes a random access memory look-up table.

20. The computer system as recited in claim 19 further comprising:

a system memory coupled to a memory controller, wherein said memory controller is configured to provide an interface to said system memory.

21. The computer system as recited in claim 18, wherein said first memory is allocated within a portion of said system memory.

22. The computer system as recited in claim 19, wherein said first memory is a frame buffer memory coupled to said graphics processor.

23. The computer system as recited in claim 18, wherein said graphics subsystem further comprises:

a display clock generator unit implemented on said second integrated circuit chip, wherein said display clock generator unit is coupled to said graphics processor and is configured to generate display timing signals for driving a video display.

24. The graphics subsystem as recited in claim 23, wherein said display timing signals include vertical and horizontal synchronization signals.

25. The computer system as recited in claim 24, wherein said graphics subsystem further comprises:

a programmable timing control register unit implemented on said second integrated circuit chip, wherein said programmable timing control register unit is coupled to said display clock generator unit and is configured to store display timing information.

26. The computer system as recited in claim 25, wherein said programmable timing control register unit includes a plurality of registers.

27. The computer system as recited in claim 26, wherein said display timing information includes display resolution information and vertical and horizontal refresh information.

28. The computer system as recited in claim 18, wherein said graphics subsystem further comprises:

a bus interface implemented on said second integrated circuit chip, wherein said bus interface is coupled to said graphics processor and is configured to receive packet-based information across a bus.

29. The computer system as recited in claim 28, wherein said graphics subsystem further comprises:

a video stream interface implemented on said second integrated circuit chip, wherein said video stream interface configured to provide video image frame data for storage in a second memory.

30. The computer system as recited in claim 29, wherein said graphics subsystem further comprises:

a graphics and video combiner unit implemented on said second integrated circuit chip, wherein said graphics and video combiner unit is coupled to said conversion unit and is configured to provide digital image information combined with video image frame data to said digital-to-analog converter circuit.

31. The computer system as recited in claim 30, wherein said graphics subsystem further comprises:

a frame synchronizer, wherein said frame synchronizer is coupled to said display clock generator unit and is configured to provide a video frame synchronization signal to said graphics and video combiner unit.

32. The computer system as recited in claim 31, wherein said graphics subsystem further comprises:

a video stream timestamp processor, wherein said video stream timestamp processor is coupled to said frame synchronizer and is configured to provide a timestamp signal to said frame synchronizer.

33. The computer system as recited in claim 32, wherein said graphics subsystem further comprises:

a video stream retriever, wherein said video stream retriever is coupled to said local video frame store memory and is configured to retrieve said video image frame data stored in said local video frame store memory and to cause said video image frame data to be provided to said graphics and video combiner unit.

34. The computer system as recited in claim 33, wherein said graphics subsystem further comprises:

a video window resizing engine, wherein said video window resizing engine is coupled to said graphics and video combiner unit and is configured to mathematically resize said video image frame data dependent upon information stored in said programmable timing control register unit.

35. The computer system as recited in claim 29, wherein said second memory is a local frame store memory implemented on said second integrated circuit chip.

36. The computer system as recited in claim 18, wherein said designated memory region is allocated within a portion of said system memory.