Same tile method

• US 6,798,421 B2
• Filed: 02/28/2002
• Issued: 09/28/2004
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: 3D Labs
• Inventors: Baldwin, David Robert
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US10/087,233
• Publication Number:
  US 20020118202A1
• Time in Patent Office: 943 Days
• Field of Search: 345/418, 345/501, 345/502, 345/530, 345/545, 345/552, 345/557, 345/560, 711/118
• US Class Current: 345/557
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.)

Claims

1. A graphics processing method, comprising the steps of:

selectably saving entire two-dimensional tiles of data, from the output of a graphics computational unit, in a dedicated same-tile buffer; and

selectably making the contents of said same-tile buffer available for a data input to said graphics computational unit.

2. The method of claim 1, wherein said tiles are square tiles of 64 pixels.

3. A graphics processing method, comprising the steps of:

(a.) selectably merging data outputs from a graphics computational unit with data retrieved from a cache; and

(b.) selectably saving two-dimensional tiles of data, from the output of said graphics computational unit, in a dedicated same-tile buffer; and

(c.) selectably making the contents of said same-tile buffer available for a data input to said graphics computational unit.

4. The method of claim 3, wherein said step (b) saves entire tiles.