Full duplex gigabit-rate transceiver front-end and method operation

• US 6,798,828 B1
• Filed: 05/12/2000
• Issued: 09/28/2004
• Est. Priority Date: 05/12/2000
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Phanse, Abhijit M.
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): PUENTE, EVA YI ZHENG
• Application Number:
  US09/570,076
• Time in Patent Office: 1,600 Days
• Field of Search: 375/219, 375/375, 375/346, 375/231, 379/406.12
• US Class Current: 375/219
• CPC Class Codes: H04B 3/145 variable equalisers
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only

Abstract

A method for equalizing a signal in a transceiver includes receiving an analog signal and adaptively equalizing the analog signal in an adaptive equalization filter to produce an analog filtered signal. The method also includes converting the analog filtered signal to a digital signal, digitally adapting the digital signal in a digital finite impulse response (FIR) filter, and modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with an output of the digital FIR filter. The method further includes providing the at least one modified digital filter coefficient of the digital FIR filter to an analog equalization controller. In addition, the method includes using the at least one modified digital filter coefficient of the digital FIR filter in the analog equalization controller to adaptively equalize the analog signal in the adaptive equalization filter.

Claims

1. For use in a high speed Ethernet local area network (LAN), a transceiver comprising:

front-end analog signal processing circuitry comprising;

a line driver capable of receiving an outgoing analog signal from a data source and transmitting said outgoing analog signal to an external cable via a transformer coupling said transceiver to said external cable;

a DC offset correction circuit capable of receiving an incoming analog signal from said transformer and reducing a DC component in said incoming analog signal;

an echo canceller capable of receiving said incoming analog signal and reducing in said incoming analog signal, an echo component of said outgoing analog signal to thereby produce a reduced-echo incoming analog signal;

an automatic gain control (AGC) circuit capable of receiving said reduced-echo incoming analog signal and amplifying said reduced-echo incoming analog signal by an adjustable gain factor to thereby produce an amplified incoming analog signal; and

an adaptive analog equalization filter capable of receiving said amplified incoming analog signal and amplifying a first high frequency component of said amplified incoming analog signal to thereby produce an analog filtered incoming signal;

an analog-to-digital converter (ADC) capable of converting said analog filtered incoming signal to a first incoming digital signal; and

digital signal processing circuitry comprising;

a digital finite impulse response (FIR) filter capable of receiving said first incoming digital signal and amplifying a second high frequency component of said first incoming digital signal to thereby produce a digital filtered incoming signal.

2. The transceiver as set forth in claim 1 further comprising:

a digital FIR controller capable of modifying at least one digital filter coefficient of said digital FIR filter according to a signal error associated with a digital output of said digital FIR filter; and

an analog equalization controller capable of modifying a first adjustable gain factor associated with said adaptive equalization filter according to a value of said at least one digital filter coefficient.

3. The transceiver as set forth in claim 2 wherein said analog equalization controller comprises:

a comparison logic circuit capable of receiving at least one digital filter coefficient from said digital FIR controller and capable of comparing said at least one digital filter coefficient with a predetermined value of a convergence threshold;

wherein said comparison logic circuit outputs a logic signal of positive one if said at least one digital filter coefficient is greater than said convergence threshold and a logic signal of negative one if said at least one digital filter coefficient is less than said convergence threshold.

4. The transceiver as set forth in claim 3 wherein said analog equalization controller further comprises:

an adder circuit having a first input coupled to an output of said comparison logic circuit;

a register capable of providing a control feedback signal to said adaptive equalization filter wherein an input of said register is coupled to an output of said adder circuit; and

a delay circuit having an input coupled to an output of said register and an output coupled to a second input of said adder circuit.

5. The transceiver as set forth in claim 1 wherein said analog equalization controller is capable of providing an increased level of analog equalization to said adaptive equalization filter when said analog equalization controller receives a digital filter coefficient from said digital FIR controller that is greater than a predetermined value of a convergence threshold.

6. The transceiver as set forth in claim 1 wherein said analog equalization controller is capable of providing a decreased level of analog equalization to said adaptive equalization filter when said analog equalization controller receives a digital filter coefficient from said digital FIR controller that is less than a predetermined value of a convergence threshold.

7. The transceiver as set forth in claim 1 wherein said digital FIR controller is capable of providing digital adaptation for said first incoming digital signal using said signal error associated with a digital output of said digital FIR filter to modify at least one digital filter coefficient to adjust signal gain for said first incoming digital signal;

and wherein said analog equalization controller is capable of providing adaptive equalization for said incoming analog signal using at least one digital filter coefficient from said digital FIR filter controller to modify at least one adjustable gain factor to adjust gain for said incoming analog signal.

8. The transceiver as set forth in claim 7 wherein said digital FIR controller and said analog equalization controller alternately operate to provide said digital adaptation for said first incoming digital signal and said adaptive equalization for said incoming analog signal until the occurrence of one of:

a convergence of digital filter coefficients of said digital FIR filter to a predetermined threshold value and a timeout.

9. A transceiver as set forth in claim 2 wherein said echo canceller comprises:

an echo canceller impedance model circuit coupled to an output of said line driver wherein said echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents a signal echo.

10. The transceiver as set forth in claim 9 wherein said echo canceller impedance model circuit has a variable impedance for generating a range of values of said echo canceller current.

11. The transceiver as set forth in claim 9 further comprising a DC offset correction controller coupled to said DC offset correction circuit, wherein said DC offset correction controller is capable of detecting an output DC offset signal component in an output signal of said front-end analog signal processing circuitry;

and in response to said detection, is capable of providing a DC offset correction signal to said DC offset correction circuit to adjust a DC offset signal component.

12. The transceiver as set forth in claim 11 wherein said DC offset correction controller is capable of detecting a positive DC offset signal component in said output signal of said front-end analog signal processing circuitry;

and in response to said detection, is capable of providing a DC offset correction signal to said DC offset correction circuit to reduce said positive DC offset signal component, and wherein said DC offset correction controller is capable of detecting a negative DC offset signal component in said output signal of said front-end analog signal processing circuitry; and

in response to said detection, is capable of providing a DC offset correction signal to said DC offset correction circuit to increase said negative DC offset signal component.

13. The transceiver as set forth in claim 11 further comprising an automatic gain control (AGC) controller coupled to said automatic gain control (AGC) circuit, wherein said AGC controller comprises:

a first circuit capable of determining an absolute value of an output signal of said front-end analog signal processing circuitry;

comparison circuitry capable of comparing said absolute value of said output signal to a pre-determined threshold value and generating a gain control signal in response to said comparison, wherein said comparison circuitry sets said gain control signal to a first gain control value when said absolute value exceeds said pre-determined threshold value and sets said gain control signal to a second gain control signal when said absolute value does not exceed said pre-determined threshold value; and

a gain adjustment circuit capable of modifying said adjustable gain factor of said AGC circuit according to said first gain control value and said second gain control value.

14. The transceiver as set forth in claim 13 wherein said comparison circuitry is capable of decrementing said gain control signal for said AGC circuit when said absolute value of said output signal is greater than said pre-determined threshold value, and wherein said comparison circuitry is capable of incrementing said gain control signal for said AGC circuit when said absolute value of said output signal is less than said pre-determined threshold value.

15. A method for equalizing a signal in a transceiver capable of operating in a high frequency local area network, said method comprising the steps of:

receiving an analog signal in said transceiver;

adaptively equalizing said analog signal in an adaptive equalization filter to produce an analog filtered signal;

converting said analog filtered signal to a digital signal;

digitally adapting said digital signal in a digital finite impulse response (FIR) filter;

modifying at least one digital filter coefficient of said digital FIR filter according to a signal error associated with an output of said digital FIR filter;

providing said at least one modified digital filter coefficient of said digital FIR filter to an analog equalization controller coupled to said adaptive equalization filter; and

using said at least one modified digital filter coefficient of said digital FIR filter in said analog equalization controller to adaptively equalize said analog signal in said adaptive equalization filter.

16. The method as set forth in claim 15 wherein the step of adaptively equalizing said analog signal in an adaptive equalizer filter to produce an analog filtered signal comprises the steps of:

providing an increased level of analog equalization to said adaptive equalization filter when said analog equalization controller receives a digital filter coefficient from said digital FIR controller that is greater than a predetermined value of a convergence threshold; and

providing a decreased level of analog equalization to said adaptive equalization filter when said analog equalization controller receives a digital filter coefficient from said digital FIR controller that is less than a predetermined value of a convergence threshold.

17. The method as set forth in claim 15 further comprising the step of:

cancelling at least one echo signal component in an incoming analog signal received by said transceiver to produce a reduced-echo incoming analog signal.

18. The method as set forth in claim 17 further comprising the steps of:

detecting a DC offset signal component in said output signal of said front-end analog signal processing circuitry; and

in response to said detection, providing a DC offset correction signal to a DC offset correction circuit in said transceiver to adjust said DC offset signal component.

19. The method as set forth in claim 18 further comprising the steps of:

determining in an automatic gain control (AGC) controller coupled to an automatic gain control (AGC) circuit in said transceiver an absolute value of an output signal of said front-end analog signal processing circuitry;

comparing in comparison circuitry of said AGC controller said absolute value of said output signal to a pre-determined threshold value;

generating a gain control signal in response to said comparison, wherein said comparison circuitry sets said gain control signal to a first gain control value when said absolute value exceeds said pre-determined threshold value and sets said gain control signal to a second gain control signal when said absolute value does not exceed said pre-determined threshold value; and

modifying in a gain adjustment circuit of said AGC controller an adjustable gain factor of said AGC circuit according to said first gain control value and said second gain control.

20. The method as set forth in claim 19 further comprising the steps of:

decrementing said gain control signal for said AGC circuit when said absolute value of said output signal is greater than a pre-determined threshold value; and

incrementing said gain control signal for said AGC circuit when said absolute value of said output signal is less than said pre-determined threshold value.