System and method for synchronizing data transfer from one domain to another by selecting output data from either a first or second storage device

• US 6,799,280 B1
• Filed: 01/04/2000
• Issued: 09/28/2004
• Est. Priority Date: 01/04/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bryant, Christopher D., Edenfield, Robin W.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): CONNOLLY, MARK A
• Application Number:
  US09/477,488
• Time in Patent Office: 1,729 Days
• Field of Search: 713/400, 713/401, 327/144, 710/21, 368/52
• US Class Current: 713/400
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

An interface circuit is disclosed for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, where the phase and frequency relationships of the first and second clock signals are known. The interface circuit comprises: 1) a flip-flop having a data input for receiving a first data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a latch having a data input coupled to the flip-flop output, a clock input for receiving a gating signal, and an output; and 3) a multiplexer having a first data input coupled to the flip-flop output, a second data input coupled to the latch output, and a selector input for selecting one of the first and second data inputs for the multiplexer output.

Claims

1. An interface circuit for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising:

a flip-flop having a data input for receiving a first data signal from a first clock domain, a clock input for receiving a first clock signal, and an output;

a latch having a data input coupled to said flip-flop output and a clock input for receiving a gating signal, and an output;

a multiplexer having a first data input coupled to said flip-flop output, a second data input coupled to said latch output, and a selector input for selecting one of said first data input or said second data input for transfer to an output of said multiplexer, wherein said first data input of said multiplexer is selected in response to a rising edge of said first clock signal being approximately in phase with a rising edge of said second clock signal; and

wherein said second clock signal and said first clock signal are derived from a common core clock.

2. The interface circuit set forth in claim 1 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

3. The interface circuit set forth in claim 1 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.

4. The interface circuit set forth in claim 1 wherein said selection signal is applied to said selector input during one clock period of said first clock signal.

5. The interface circuit set forth in claim 4 wherein said gating signal is applied to said latch clock input when said selection signal is applied to said selector input and during a low phase of said first clock signal.

6. The interface circuit set forth in claim 1 further comprising a second interface circuit for synchronizing the transfer of data from said second clock domain to said first clock domain, said second interface circuit comprising:

a flip-flop having a data input for receiving a first data signal from said second clock domain, a clock input for receiving said second clock signal, and an output;

a latch having a data input coupled to said flip-flop output, a clock input for receiving said first clock signal, and an output; and

a multiplexer having a first data input coupled to said flip-flop output, a second data input coupled to said latch output, and a selector input for selecting one of said first data input and said second data input for transfer to an output of said multiplexer.

7. A computer system comprising:

a pipelined processor having dual integer and dual floating point execution units, separate load/store and branch units, an LI instruction cache and an LI data cache;

system memory for storing data or instructions;

a core clock;

an interface circuit for synchronizing the transfer of data from a first clock domain driven by a first clock signal in said processor to a second clock domain driven by a second clock signal in said processor, the interface circuit comprising;

a flip-flop having a data input for receiving a first data signal from a first clock domain, a clock input for receiving said first clock signal, and an output;

a latch having a data input coupled to said flip-flop output, a clock input for receiving a dating signal, and an output;

a multiplexer having a first data input coupled to said flip-flop output, a second data input coupled to said latch output, and a selector input for selecting one of said first data input or said second data input for transfer to an output of said multiplexer, wherein said first data input of said multiplexer is selected in response to a rising edge of said first clock signal being approximately in phase with a rising edge of said second clock signal; and

wherein said second clock signal and said first clock signal are derived from said core clock.

8. The computer system set forth in claim 7 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

9. The computer system set forth in claim 8 wherein said selection signal is applied to said selector input during one clock period of said first clock signal.

10. The computer system set forth in claim 7 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.

11. The computer system set forth in claim 10 wherein said gating signal is applied to said latch clock input when said selection signal is applied to said selector input and during a low phase of said first clock signal.

12. The computer system set forth in claim 7 further comprising a second interface circuit for synchronizing the transfer of data from said second clock domain to said first clock domain, said second interface circuit comprising:

a flip-flop having a data input for receiving a first data signal from said second clock domain, a clock input for receiving said second clock signal, and an output;

a latch having a data input coupled to said flip-flop output, a clock input for receiving said first clock signal, and an output; and

a multiplexer having a first data input coupled to said flip-flop output, a second data input coupled to said latch output, and a selector input for selecting one of said first data input and said second data input for transfer to an output of said multiplexer.

13. For use in a processor, a method for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal comprising the steps of:

receiving a first data signal from the first clock domain into a flip-flop having a data input, a clock input for receiving the first clock signal, and an output;

sampling the output of the flip-flop using a latch having a data input coupled to the flip-flop output, a clock input for receiving a gating signal, and an output; and

selecting one of the output of the flip-flop and the output of the latch using a multiplexer having a first data input coupled to the flip-flop output, a second data input coupled to the latch output, and a selector input for selecting one of the first data input or said second data input for transfer to an output of the multiplexer;

wherein a selection signal applied to the selector input selects the first data input of the multiplexer when a rising edge of the first clock signal is approximately in phase with a rising edge of the second clock signal.

14. The method set forth in claim 13 wherein the selection signal is applied to the selector input during one clock period of the first clock signal.

15. The method set forth in claim 14 wherein the gating signal is applied to the latch clock input when the selection signal is applied to the selector input and during a low phase of the first clock signal.