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Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET

  • US 6,800,509 B1
  • Filed: 06/24/2003
  • Issued: 10/05/2004
  • Est. Priority Date: 06/24/2003
  • Status: Active Grant
First Claim
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1. A process for forming a trench-gate power MOSFET, comprising the steps of:

  • forming a trench deep into a drift layer of a first conductivity type above a substrate of said first conductivity type;

    forming a first oxide on a surface of said trench;

    depositing a nitride on a surface of said first oxide;

    forming a second oxide filled in said trench;

    etching said second oxide for leaving a thick oxide at a bottom of said trench;

    etching said nitride for remaining a part of said nitride at said bottom of said trench;

    forming a gate oxide on a sidewall of said trench;

    forming a gate conductor filled in said trench;

    forming a well region of a second conductivity type opposite to said first conductivity type adjacent to said sidewall of said trench;

    forming a source region of said first conductivity type on said well region;

    forming an insulator for covering on said gate conductor and a surface of said source region; and

    depositing a metal for electrically connecting said source region with said well region.

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