Inter-tile buffer system for a field programmable gate array

• US 6,800,884 B1
• Filed: 12/30/2002
• Issued: 10/05/2004
• Est. Priority Date: 12/30/2002
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Lien, Jung-Cheun, Liu, Tong, Feng, Sheng
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): GREENE, PERSHELLE L
• Application Number:
  US10/334,393
• Time in Patent Office: 645 Days
• Field of Search: 257/202, 257/208, 257/209, 326/41
• US Class Current: 257/209
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus and a vertical bus. A horizontal buffer is located between each column of field programmable gate array tiles and is coupled to the primary routing structure. A vertical buffer is located between each row of field programmable gate array tiles and is coupled to the primary routing structure.

Claims

1. A field programmable gate array, said field programmable gate array comprising:

a plurality of field programmable gate array tiles arranged in an array of rows and columns, each field programmable gate array tile comprising;

a plurality of functional groups wherein each of said plurality of functional groups is configured to receive at least one input signal, and generate at least one output signal,

a plurality of interface groups, wherein each of said plurality of interface groups is configured to selectively transfer signals between said primary routing structure and circuitry external to the field programmable gate array tile, and

a primary routing structure including a horizontal bus and a vertical bus wherein the primary routing structure is coupled to said functional groups and interface groups, and is configured to receive signals from said plurality of functional groups and said plurality of interface groups and provide signals between said plurality of functional groups and said plurality of interface groups;

a horizontal buffer connecting a primary routing structure in a first one of said plurality of field programmable gate array tiles in a first column and to a primary routing structure in a second one of said plurality of programmable gate array tiles in a second column adjacent to said first column; and

a vertical buffer connecting a primary routing structure in a first one of said plurality of field programmable gate array tiles in a first row to a primary routing structure in a second one of said plurality of programmable gate array tiles in a second row adjacent to said first row.

2. The field programmable gate array of claim 1, said horizontal buffer comprising at least two, three-state buffers arranged in a bi-directional configuration, between said first one of said plurality of field programmable gate array tiles and said second one of said plurality of field programmable gate array tiles.

3. The field programmable gate array of claim 2, wherein said horizontal buffer is coupled to said horizontal bus in the primary routing structure in a first one of said plurality of field programmable gate array tiles in the first column and to said horizontal bus of the primary routing structure in the second one of said plurality of programmable gate array tiles in the second column.

4. The field programmable gate array of claim 1, wherein said horizontal buffer further comprises at least two, five-to-one multiplexers arranged in a bi-directional configuration between said first one of said plurality of field programmable gate array tiles and said second one of said plurality of field programmable gate array tiles.

5. The field programmable gate array of claim 3, wherein said horizontal bus of said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

a horizontal, segmented bus; and

a horizontal, non-segmented bus, coupled to said horizontal buffer.

6. The field programmable gate array of claim 5, wherein said horizontal, non-segmented bus is configured to transfer signals between said plurality of field programmable gate array tiles.

7. The field programmable gate array of claim 5, wherein said horizontal bus of said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

a cross-bus buffer coupling said horizontal, non-segmented bus to said horizontal, segmented bus.

8. The field programmable gate array of claim 6, wherein said horizontal bus of said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

an inter-bus buffer coupled to said horizontal, segmented bus.

9. The field programmable gate array of claim 8, wherein said cross-bus buffer comprises a bidirectional, three-state transistor configuration and said inter-bus buffer comprises a bidirectional, three-state transistor configuration.

10. The field programmable gate array of claim 1, said vertical buffer comprising at least two, three-state buffers arranged in a bi-directional configuration, between said first one of said plurality of field programmable gate array tiles in said first row and said second one of said plurality of field programmable gate array tiles in said second row.

11. The field programmable gate array of claim 10, wherein said vertical buffer is coupled to said vertical bus in the primary routing structure in a first one of said plurality of field programmable gate array tiles in the first row and to said horizontal bus of the primary routing structure in the second one of said plurality of programmable gate array tiles in the second row.

12. The field programmable gate array of claim 11, wherein each said vertical buffer further comprises at least two, five-to-one multiplexers arranged in a bi-directional configuration between said first one of said plurality of field programmable gate array tiles in said first row and said second one of said plurality of field programmable gate array tiles in said second row.

13. The field programmable gate array of claim 11, wherein said vertical bus of said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

a vertical, segmented bus; and

a vertical, non-segmented bus, said vertical, non-segmented bus coupled to said vertical buffer.

14. The field programmable gate array of claim 13, wherein said vertical, non-segmented bus is configured to transfer signals between said plurality of field programmable gate array tiles.

15. The field programmable gate array of claim 14, said vertical bus of f said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

a cross-bus buffer coupling said vertical, non-segmented bus to said vertical, segmented bus.

16. The field programmable gate array of claim 15, said vertical bus of f said primary routing structure of each of said plurality of filed programmable gate array tiles further comprises:

an inter-bus buffer coupled to said vertical, segmented bus.

17. The field programmable gate array of claim 16, wherein said cross-bus buffer comprises a bidirectional, three-state transistor configuration and said inter-bus buffer comprises a bidirectional, three-state transistor configuration.