Method for fabricating semiconductor device

• US 6,800,907 B2
• Filed: 12/30/2002
• Issued: 10/05/2004
• Est. Priority Date: 05/16/2002
• Status: Expired due to Term

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Jae-Ok, Kim, Woo-Jin, Oh, Jong-Hyuk
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US10/330,341
• Publication Number:
  US 20030216021A1
• Time in Patent Office: 645 Days
• Field of Search: 438/301, 438/592, 438/300, 438/353, 438/595
• US Class Current: 257/356
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a method for fabricating a semiconductor device capable of suppressing stresses concentrated at bottom corners of a gate electrode as simultaneously as preventing an oxidation of a metal included in a gate electrode. The inventive method includes the steps of: forming a gate oxide layer on a substrate; forming a gate electrode including at least one metal layer on the gate oxide layer; forming an oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer; and etching selectively the densified oxide layer so as to form an oxide spacer on the lateral sides of the gate electrode.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

forming a gate oxide layer on a substrate;

forming a gate electrode including at least one metal layer on the gate oxide layer;

forming a PETEOS oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer;

densifying the PETEOS oxide layer by performing a thermal process after forming the PETEOS oxide layer; and

etching selectively the densified PETEOS oxide layer so as to form an oxide spacer on the lateral sides of the gate electrode.

2. The method as recited in claim 1, wherein the step of forming the PETEOS oxide layer used for an oxide spacer proceeds with a plasma enhanced chemical deposition technique using a source gas including tetra ethyl ortho silicate (TEOS).

3. The method as recited in claim 1, wherein the PETEOS oxide layer is formed at a temperature ranging from about 300°

C. to about 600°

C.

4. The method as recited in claim 2, wherein the source gas further includes O₂ or O₃.

5. The method as recited in claim 1, wherein the densified PETEOS oxide layer is formed to a thickness in a range from about 50 Å

to about 500 Å

.

6. The method as recited in claim 1, wherein the step of densifying the PETEOS oxide layer is carried cut at a pressure ranging from about 1.0 Torr to about 5.0 Torr.

7. The method as recited in claim 1, wherein the thermal process is performed at a temperature ranging from about 700°

C. to about 1000°

C. in an atmosphere of either inert gas or reducing gas.

8. The method as recited in claim 1, wherein the step of forming the gate electrode includes further the steps of:

forming sequentially a polysilicon layer and a metal layer on the gate oxide layer;

etching selectively the metal layer and the polysilicon layer; and

oxidizing selectively lateral sides of the polysilicon layer.

9. The method as recited in claim 2, wherein the step of forming the oxide spacer further includes the steps of:

forming a nitride on the densified oxide layer; and

forming a nitride spacer through an etchback process to the nitride as simultaneously as forming the oxide spacer on the lateral sides of the gate electrode.

10. A method for fabricating a semiconductor device, comprising the steps of:

forming a gate oxide layer on a substrate;

forming a gate electrode by stacking a silicon based conductive layer and metal layer on the gate oxide layer;

forming a PETEOS oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer;

forming an oxide spacer on lateral sides of the gate electrode through an etching back process to the PETEOS oxide layer; and

oxidizing selectively lateral sides of the silicon based conductive layer, contacting to the oxide spacer, through a thermal process.

11. The method as recited in claim 10, wherein the step of oxidizing selectively the lateral sides of the silicon based conductive layer is proceeded at a temperature in a range from about 700°

C. to about 900°

C. in an atmosphere of H₂ with use of H₂O as an oxidation agent.

12. The method as recited in claim 10, wherein the step of oxidizing selectively the lateral sides of the silicon based conductive layer includes the steps of:

depositing a nitride on the substrate including the oxide spacer through a low pressure chemical deposition technique; and

forming a nitride spacer on the oxide spacer through an etchback process to the nitride.

13. The method as recited in claim 10, wherein the PETEOS oxide layer is formed at a temperature ranging from about 300°

C. to about 600°

C.

14. The method as recited in claim 10, wherein the step of forming the PETEOS oxide layer proceeds with a plasma enhanced chemical deposition techniques using a source gas including TEOS.

15. The method as recited in claim 10, further comprising the step of densifying the PETEOS oxide layer through a thermal process after forming the PETEOS oxide layer.