Multiple oxide thicknesses for merged memory and logic applications
First Claim
1. A semiconductor device comprising:
- a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide.
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Abstract
Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
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Citations
29 Claims
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1. A semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 17, 18, 19, 20)
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8. A semiconductor device comprising:
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a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (111) crystalline plane orientation, the logic device having a logic gate separated from the top surface by a logic gate; and
a flash memory cell formed on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystalline plane orientation, the flash memory cell having a flash gate separated from the trench wall by a flash gate oxide, wherein a thickness of the logic gate oxide is different from a thickness of the flash gate oxide. - View Dependent Claims (9, 10, 11)
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12. A semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide, wherein the top gate oxide thickness is approximately 70 Angstroms, and wherein the top device has an operating voltage of less than 2.5 volts; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (13, 14)
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15. A semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein the trench gate oxide thickness is approximately 100 Angstroms, wherein the trench device has an operating voltage of less than 3.5 volts, and wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (16)
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21. The semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide, and wherein the top gate oxide thickness is approximately 70 Angstroms; and
a trench device formed on the trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein the trench gate oxide thickness is approximately 100 Angstroms, and wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (22)
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23. A semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide, wherein the top device is a logic device, and wherein the top device has an operating voltage of less than 2.5 volts; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the trench gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (24)
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25. A semiconductor device comprising:
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a top device formed on a top surface on a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein the trench device is a DRAM cell, wherein the trench device has an operating voltage of less than 3.5 volts, and wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (26, 27, 28, 29)
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Specification