CMOS integration sensor with fully differential column readout circuit for light adaptive imaging

• US 6,801,258 B1
• Filed: 03/16/1999
• Issued: 10/05/2004
• Est. Priority Date: 03/16/1998
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata, Fossum, Eric R., Zhou, Zhimin
• Primary Examiner(s): Vu, Ngoc-Yen, Vu, Ngoc-Yen
• Assistant Examiner(s): Henn, Timothy J.
• Application Number:
  US09/268,879
• Time in Patent Office: 2,030 Days
• Field of Search: 348/294, 348/295, 348/297, 348/300, 348/302, 348/307, 348/308, 250/208.1
• US Class Current: 348/302
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An imager that is better suited for low-light detection capability. In accordance with a preferred embodiment, the imager may be easily configured to provide an imager having multi-resolution capability where SNR can be adjusted for optimum low-level detectibility. Multi-resolution signal processing functionality is provided on-chip to achieve high speed imaging, as well as low power consumption. The imager architecture employs an improved pixel binning approach with fully differential circuits situated so that all extraneous and pick-up noise is eliminated. The current implementation requires no frame transfer memory, thereby reducing chip size. The reduction in area enables larger area format light adaptive imager implementations.

Claims

1. An active pixel sensor (APS) imager comprising:

a semiconductor substrate;

a pixel sensor array of (x) rows and (y) columns of pixels, formed on said substrate;

a neighborhood selector, formed on said substrate, selecting a kernel of n by m pixels in said array;

a column integrator array, formed on said substrate, defined by a plurality of column integrators, said column integrators coupled to corresponding columns of pixels and operating to differentially integrate pixel signals on each selected row for each pixel block;

a column memory array, formed on said substrate, defined by an array of differentially integrated capacitor circuits which sum and hold the differentially integrated pixel signals from n selected column integrators to generate, at the end of a row summing cycle, a row summed charge signal indicative of said n pixels in said row; and

a global output integrator, formed on said substrate, receiving said row summed charge signal for each of said m columns, and generating a pixel block summed output by summing said (m) signals.

2. The imager of claim 1, wherein said pixel sensor array includes a plurality of pixels, each of which include a photosensor element, and a buffer.

3. The APS imager of claim 1, wherein said neighborhood selector is variable, enabling multiple resolutions of modes.

4. The APS imager of claim 1, wherein each column integrator is a differential circuit including a pair of integrating capacitors configured to substantially eliminate extraneous and pick-up noise.

5. The APS imager of claim 4, wherein each capacitor circuit is a fully differential circuit including first and second summing capacitors said first summing capacitor for a signal level, and said second summing capacitor for a reset level.

6. The APS imager of claim 4, wherein each global output integrator is a fully differential circuit including a pair of opamps.

7. The APS imager of claim 1, wherein each pixel block is a square block.

8. The APS imager of claim 1, further comprising column select logic and row select logic generating addressing and timing control signals on the basis of a presently selected resolution mode.

9. The APS imager of claim 1, further comprising column select logic and row select logic generating addressing and timing control signals on the basis of a presently selected pixel block size.

10. A method of operating a pixel sensor, comprising:

obtaining a pixel sensor imager including a pixel sensor array of (x) rows and (y) columns of pixels;

defining a sub block of pixels, of (n) rows and (m) columns of neighboring row and column pixels, where n is less than x and m is less than y;

differentially integrating pixel signals on each of said n rows, using a column integrator array defined by an array of column integrators, said column integrators coupled to said columns of pixels;

summing and holding, said n rows, using a differential integrator, to generate at the end of a row summing cycle, an (n) row summed charge signal; and

generating a summed output, using a global output integrator, by summing (m) of the n-row charge signals at the end of a column summing cycle.

11. The method of claim 10, further comprising generating addressing and timing control signals on the basis of a presently selected resolution mode.

12. The APS imager of claim 10, further comprising column select logic and row select logic generating addressing and timing control signals on the basis of a presently selected pixel block size.