Acquisition timing loop for read channel

• US 6,801,380 B1
• Filed: 03/11/2003
• Issued: 10/05/2004
• Est. Priority Date: 09/12/2000
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): Kapadia, Varsha A.
• Application Number:
  US10/385,977
• Time in Patent Office: 574 Days
• Field of Search: 360/65, 360/46
• US Class Current: 360/65
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10027 adjusting the signal strength during recording or reproduction, e.g. variable gain amplifiers optimum power control for optical discs G11B7/125
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: G11B 5/012 Recording on, or reproducing or erasing from, magnetic disks G11B17/00, G11B19/00 take precedence
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

A signal from a storage medium is processed in a data channel to form digital data. An amplifier and a sampler convert the storage medium signal into a timed sample sequence. A first equalizer and adjuster operates to equalize the timed sample sequence and to adjust the gain of the amplifier and timing of the sampler in a preamble segment of the signal. A second equalizer and adjuster circuit to equalize the timed sample sequence for detection and to adjust the gain of the amplifier and the timing of the sampler operates in a user data segment of the signal. An FIR equalizing filter in the second equalizer and adjuster circuit is controlled by a set of parameters to accurately equalize a large range of waveforms in the user data segment of the signal and an FIR equalizing filter in the first equalizer and adjuster circuit is controlled by a smaller set of related set of parameters adapted to accommodate rapid adjustment during synchronization in the preamble segment of the signal.

Claims

1. A signal processing circuit, comprising:

means responsive to an input signal for forming a timed sample sequence;

first means responsive to the timed sample sequence during a first segment of the signal for equalizing the timed sample sequence and adjusting the timed sample sequence forming means; and

second means responsive to the timed sample sequence during a second segment of the signal for equalizing the timed sample sequence and adjusting the timed sample sequence forming means.

2. A signal processing circuit according to claim 1,

wherein the first means includes first filtering means responsive to a set of first parameter signals for equalizing the timed sample sequence during the first segment of the signal and first control means responsive to the equalized timed sample sequence for forming timing and gain adjusting signals to control the timed sample sequence forming means during the first signal segment, and

wherein the second means includes second filtering means responsive to a set of second parameter signals for equalizing the timed sample sequence during the second segment of the signal, and second control means responsive to the equalized timed sample sequence for forming timing and gain adjusting signals to control the timed sample sequence forming means during the second signal segment.

3. A signal processing circuit according to claim 2, wherein a number of first parameter signals is smaller than a number of second parameter signals.

4. A signal processing circuit according to claim 3, wherein the first filtering means and the second filtering means form substantially the same equalized timed sample sequence for the signal of the first signal segment.

5. A signal processing circuit according to claim 3, wherein each first parameter signal is a linear combination of at least some of the second parameter signals.

6. A signal processing circuit according to claim 5, wherein the number of first parameter signals is at least two.

7. A signal processing circuit according to claim 5, wherein the second filtering means includes second FIR filtering means and the second parameter signals includes a set of second FIR equalizer coefficient signals c0, c1, c2, . . . cn, cn+1, and

wherein the first filtering means includes first FIR filtering means and the first parameter signals includes a set of first FIR equalizer coefficient signals

8. A signal processing circuit according to claim 7, wherein the first FIR equalizer coefficient signals for forming a substantially same equalized timed sample sequence as the second FIR equalizer coefficient signals for the signal of the first signal segment are

9. A signal processing circuit according to claim 8, wherein the first FIR equalizer coefficient signals are formed in an initial portion of the first signal segment.

10. A signal processing circuit according to claim 7, wherein the first signal segment includes a 4T sinusoid pattern and the timed sample sequence during the first signal segment includes a sequence of samples having values (s0, s1, −

s0, −

s1, . . . ) and a target output timed signal sequence of the first FIR equalizer for the first signal segment is of the form (xo, x1, −

x0, −

x1, . . . ) and wherein the first FIR equalizer coefficient signals to provide a substantially same response as the second FIR equalizer filter to the first signal segment are

11. A signal processing circuit according to claim 10, wherein the first FIR equalizer coefficient signals are formed in an initial portion of the first signal segment.

12. A signal processing circuit according to claim 2, wherein the timed sample sequence forming means comprises amplifying means and sampling means, the first control means comprises first gain control means responsive to the equalized timed sample sequence for adjusting a gain of the amplifying means and first timing control means responsive to the equalized timed sample sequence for adjusting a timing of the sampling means during the first signal segment and the control means comprises second gain control means responsive to the equalized timed sample sequence for adjusting the gain of the amplifying means and second timing control means responsive to the equalized timed sample sequence for adjusting the timing of the sampling means during the second signal segment.

13. A signal processing circuit according to claim 1, wherein the first signal segment is an acquisition signal and the second signal segment is a data signal.

14. A method of processing an input signal, comprising the steps of:

a. forming a timed sample sequence responsive to the input signal;

b. equalizing the timed sample sequence;

c. in response to step b adjusting step a during a first segment of the signal;

d. equalizing the timed sample sequence; and

e. in response to step d adjusting step a during a second segment of the signal.

15. A method according to claim 14,

wherein step b comprises the step of:

f. filtering the first signal segment in accordance with a first set of parameters;

wherein step c comprises the step of

g. forming timing and gain adjusting signals in a first control responsive to step f; and

wherein step d comprises the step of;

h. filtering the second signal segment in accordance with a second set of parameters; and

wherein step e comprises the step of;

i. forming of the timed sample sequence in a second control responsive to the step h.

16. A method according to claim 15, wherein a number of first parameter signals is smaller than a number of second parameter signals.

17. A method according to claim 16, steps f and h form substantially the same equalized timed sample sequence for the signal of the first signal segment.

18. A method according to claim 16, wherein each first parameter signal is a linear combination of at least some of the second parameter signals.

19. A method according to claim 18, wherein the number of first parameter signals is at least two.

20. A method according to claim 18, the second parameter signals includes a set of second FIR coefficient signals c0, c1, c2, . . . cn, cn+1, and

wherein the first parameter signals includes a set of first FIR equalizer coefficient signals

21. A method according to claim 20, wherein the first FIR equalizer coefficient signals for forming a substantially same equalized timed sample sequence as the second FIR equalizer coefficient signals for the signal of the first signal segment are

22. A method according to claim 21, wherein the first FIR equalizer coefficients are formed in an initial portion of the first signal segment.

23. A method according to claim 21, wherein the first signal segment is an acquisition signal and the second signal segment is a data signal.

24. A signal processing circuit comprising:

a converter responsive to an input signal to form a timed sample sequence;

a first processing circuit responsive to the timed sample sequence during a first segment of the signal for equalizing the timed sample sequence and adjusting the converter; and

a second processing circuit responsive to the timed sample sequence during a second segment of the signal for equalizing the timed sample sequence and adjusting the converter.

25. A signal processing circuit according to claim 24, wherein the first signal segment is an acquisition signal and the second signal segment is a data signal.

26. A signal processing circuit according to claim 24,

wherein the first processing circuit includes a first filter responsive to a set of first parameter signals for equalizing the timed sample sequence during the first segment of the signal and a first control responsive to the equalized timed sample sequence for forming timing and gain adjusting signals to control the converter for forming the timed sample sequence during the first signal segment, and

wherein the second processing circuit includes a second filter responsive to a set of second parameter signals for equalizing the timed sample sequence during the second segment of the signal, and a second control responsive to the equalized timed sample sequence for forming timing and gain adjusting signals to control the converter for forming the timed sample sequence during the second signal segment.

27. A signal processing circuit according to claim 26, wherein a number of first parameter signals is smaller than a number of second parameter signals.

28. A signal processing circuit according to claim 27, wherein the first filter and the second filter form substantially the same equalized timed sample sequence for the signal of the first signal segment.

29. A signal processing circuit according to claim 27, wherein each first parameter signal is a linear combination of at least some of the second parameter signals.

30. A signal processing circuit according to claim 29, wherein the number of first parameter signals is at least two.

31. A signal processing circuit according to claim 29, wherein the second filter includes a second FIR filter and the second parameter signals includes a set of second FIR equalizer coefficient signals c0, c1, c2, . . . cn, cn+1 for controlling the second FIR filter, and

wherein the first filter includes a first FIR filter and the first parameter signals include a set of first FIR equalizer coefficient signals

32. A signal processing circuit according to claim 31, wherein the first FIR equalizer coefficient signals for forming a substantially same equalized timed sample sequence as the second FIR equalizer coefficient signals for the signal of the first signal segment are

 

K0=c0−

c2+c4−

c6 . . . +cn−

2−

cn and

33. A signal processing circuit according to claim 32, wherein the first FIR equalizer coefficients are formed in an initial portion of the first signal segment.

34. A signal processing circuit according to claim 32, wherein the first signal segment includes a 4T sinusoid pattern and the timed sample sequence during the first signal segment includes a sequence of samples having values (s0, s1, −

s0, −

s1, . . . ) and a target output timed signal sequence of the first FIR equalizing filter for the first signal segment is of the form (xo, x1, −

x0, −

x1, . . . ) and wherein the first FIR equalizer coefficient signals to provide a substantially same response as the second FIR equalizing filter to the first signal segment are

35. A signal processing circuit according to claim 34, wherein the first FIR equalizer coefficients are formed in an initial portion of the first signal segment.

36. A signal processing circuit according to claim 26, wherein the converter comprises an amplifier and sampler, the control comprises a first timing control responsive to the equalized timed sample sequence in the first signal segment for adjusting the timing of the sampler and a first gain control for adjusting the gain of the amplifier and the second control comprises a second timing control responsive to the equalized timed sample sequence in the first signal segment for adjusting the timing of the sampler and a second gain control for adjusting the gain of the amplifier.