Memory cell isolation

• US 6,801,450 B2
• Filed: 05/22/2002
• Issued: 10/05/2004
• Est. Priority Date: 05/22/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Perner, Frederick A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Pham, Ly Duy
• Application Number:
  US10/151,914
• Publication Number:
  US 20030218906A1
• Time in Patent Office: 867 Days
• Field of Search: 365/158, 365/173, 365/177, 365/179, 365/55, 365/72, 365/66, 365/175, 365/180, 365/209
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Claims

1. A memory cell, comprising:

an isolation element including;

a first layer doped with a first type of charge,

a second layer positioned adjacent to the first layer and doped with a second type of charge,

a third layer positioned adjacent to the second layer and doped with the first type of charge, the first, second and third layers being configured as a first transistor and

a fourth layer positioned adjacent to the third layer and doped with the second type of charge, the second, third and fourth layers being configured as a second transistor and wherein the first and second transistors are configured so that the second layer is a base for the first transistor and a collector for the second transistor and the third layer is a collector for the first transistor and a base for the second transistor and the fourth layer is an emitter of the second transistor;

a resistive component electrically connected to an emitter of the first transistor of the isolation element, the resistive component having at least two resistive states;

a bit line electrically connected to the resistive component; and

a word line electrically connected to the fourth layer.

2. The memory cell of claim 1, wherein the first type of charge is a negative charge and the second type of charge is a positive charge.

3. The memory cell of claim 1, wherein the resistive component comprises a magnetic random access memory (MRAM) cell.

4. The memory cell of claim 3, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ).

5. The memory cell of claim 1, wherein the resistive component is electrically connected in series with the isolation element.

6. The memory cell of claim 1, wherein the first layer, second layer, third layer, and fourth layer comprise thin-film layers.

7. A memory array, comprising:

a plurality of bit lines;

a plurality of word lines intersecting the plurality of bit lines at a plurality of cross points; and

a plurality of memory cells, wherein a memory cell in the plurality of memory cells is located at a cross point of a first word line and a first bite line, and wherein the memory cell includes;

an isolation element including;

a first layer doped with a first type of charge,

a second layer positioned adjacent to the first layer and doped with a second type of charge,

a third layer positioned adjacent to the second layer and doped with the first type of charge, the first, second and third layers being configured as a first transistor and

a fourth layer positioned adjacent to the third layer and doped with the second type of charge, the second, third and fourth layers being configured as a second transistor and wherein the first and second transistors are configured so that the second layer is a base for the first transistor and a collector for the second transistor and the third layer is a collector for the first transistor and a base for the second transistor and the fourth layer is an emitter of the second transistor; and

a resistive component electrically connected to an emitter of the first transistor of the isolation element, the resistive component having at least two resistive states,

wherein one of the bit lines is electrically connected to the resistive component and one of the word lines is electrically connected to the fourth layer of the resistive component.

8. The memory array of claim 7, wherein the resistive component comprises a magnetic random access memory (MRAM) cell.

9. The memory cell array of claim 8, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ).

10. The memory array of claim 7, further comprising an electrical switch, electrically connected in series with the isolation element and located between the first bit line and the first word line.

11. The memory array of claim 7, further comprising a first voltage source electrically connected to the first word line, and a second voltage source electrically connected to the first bit line.

12. A memory cell arranged between a first conductor and a second conductor, comprising:

means for varying the resistance between the first and second conductors; and

means for electrically isolating the means for varying the resistance, the means for electrically isolating including;

a first layer means doped with a first type of charge,

a second layer means positioned adjacent to the first layer and doped with a second type of charge,

a third layer means positioned adjacent to the second layer and doped with the first type of charge, the first, second and third layers means being configured as a first transistor and

a fourth layer means positioned adjacent to the third layer and doped with the second type of charge, the second, third and fourth layers means being configured as a second transistor and wherein the first and second transistors are configured so that the second layer means is a base for the first transistor and a collector for the second transistor and the third layer means is a collector for the first transistor and a base for the second transistor and the fourth layer means is an emitter of the second transistor;

a bit line electrically connected to means for varying resistance; and

a word line electrically connected to the fourth layer means.

13. The memory cell of claim 12, wherein the first type of charge is a negative charge and the second type of charge is a positive charge.

14. The memory cell of claim 12, wherein the means for varying the resistance comprises a magnetic random access memory (MRAM) cell.

15. The memory cell of claim 14, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ).

16. The memory cell of claim 12, wherein the means for varying the resistance is electrically connected in series with the means for electrically isolating.

17. The memory cell of claim 12, wherein the first layer means, second layer means, third layer means, and fourth layer means comprise thin-film layers.

18. The memory cell of claim 12, further comprising switch means for selectively allowing current flow between the first and second conductors.