Arrangement with a microprocessor

• US 6,801,956 B2
• Filed: 11/13/2001
• Issued: 10/05/2004
• Est. Priority Date: 11/15/2000
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Koenig, Kurt, Feuser, Markus
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US10/014,862
• Publication Number:
  US 20020103944A1
• Time in Patent Office: 1,057 Days
• Field of Search: 235/375, 235/451, 235/492, 713/500, 710/2, 710/10-14, 710/19, 710/100, 710/104, 710/301, 710/313, 710/316
• US Class Current: 710/14
• CPC Class Codes: G06F 3/002 Specific input/output arrangements not covered by G06F3/01 - G06F3/16 other optical apparatus G02B27/00
• CPC Class Codes: G06K 19/07733 the record carrier containing at least one further contact interface not conform ISO-7816

Abstract

An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

Claims

1. An arrangement comprising:

a microprocessor which is connected to at least a USB interface and an ISO interface for exchanging data signals;

a selection unit within the microprocessor configured to select between the USB and ISO interfaces; and

a switching unit within the microprocessor configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

2. An arrangement as claimed in claim 1, wherein the microprocessor is formed for use in a chip card.

3. An arrangement as claimed in claim 1, wherein the selection unit selects the ISO interfaces if a clock signal applied to the microprocessor oscillates within a predetermined frequency range, and selects the USB interface if the clock signal applied to the microprocessor does not oscillate within the predetermined frequency range.

4. An arrangement as claimed in claim 1, wherein the the ISO interfaces is formed in accordance with ISO14443 and/or in accordance with ISO7816.

5. An arrangement as claimed in claim 2, further comprising an internal clock generation circuit configured to generate an internal clock signal in accordance with the USB interface if the clock signal applied to the microprocessor does not oscillate within the predetermined frequency range.

6. An arrangement as claimed in claim 1, wherein the switching unit is configured to switch from the USB interface to the ISO interface in response to detection of an external reset signal associated with the ISO interface.

7. An arrangement as claimed in claim 1, wherein the switching unit is configured switch from the ISO interface to the USB interface in response to detection that the USB interface is active.

8. An arrangement as claimed in claim 7, wherein detection that the USB interface is active is derived from D+ and D−

data signals associated with USB interface.