Method and apparatus for memory control circuit

• US 6,801,979 B1
• Filed: 02/14/2002
• Issued: 10/05/2004
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro
• Primary Examiner(s): McLean-Mayo, Kimberly
• Application Number:
  US10/077,647
• Time in Patent Office: 964 Days
• Field of Search: 711/5, 711/103, 711/154, 365/189.04, 365/189.05, 365/189.03, 365/230.01, 365/189.01
• US Class Current: 711/5
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register. When the data of the second data address is being accessed, the data in the first page register is transferred to a second page register. When the operation to read the data from the second data address is completed, the data can be placed in the first register. The data in the second page register can be rapidly transferred to a latch and on to a bus. In this manner, there is always space made available for the data read. Similarly, in a write operation, data is transferred from the data bus to the second page register and then to the first page register. The data in the first register is written into the memory array.

Claims

1. A method of reading from a nonvolatile memory array comprising the steps of:

providing a first page register, coupled to the nonvolatile memory array, for buffering data that is to be read from the nonvolatile memory array;

receiving a first address identifying a first location within the nonvolatile memory array wherein a first data is to be read;

providing a second page register, coupled to the nonvolatile memory array, for buffering data that is to be read from the nonvolatile memory array;

receiving a second address identifying a second location within the nonvolatile memory array wherein a second data is to be read;

latching said first and second addresses in a set of address latches, coupled to the nonvolatile memory array, said set of address latches having at least a first address latch for receiving said first address and a second address latch for receiving said second address for addressing the nonvolatile memory array;

operating said page registers and said address latches using a state machine;

decoding said received first and second addresses;

while receiving the second address, reading the first location of the nonvolatile memory array;

storing the read first location in the first page register;

reading the second location of the memory array;

while reading the second location, receiving a third address for identifying a third location within the nonvolatile memory array where a third data is to be read, thereby creating a pipe-lining effect so as to expedite the performance of read operations of the nonvolatile memory array; and

checking the number of read operations to be performed, and if a predetermined number of read operations has not been performed, continuing to the step of receiving a first address.

2. A method of writing to a nonvolatile memory array comprising the steps of:

providing a first page register, coupled to the nonvolatile memory array, for buffering data that is to be written to the nonvolatile memory array;

receiving a first address identifying a first location within the nonvolatile memory array wherein a first data is to be written;

providing a second page register, coupled to the nonvolatile memory array, for buffering data that is to be written to the nonvolatile memory array;

receiving a second address identifying a second location within the nonvolatile memory array wherein a second data is to be written;

latching said first and second addresses in a set of address latches, coupled to the nonvolatile memory array, said set of address latches having at least a first address latch for receiving said first address and a second address latch for receiving said second address for addressing the nonvolatile memory array;

operating said page registers and said address latches using a state machine;

decoding said received first and second addresses;

while the receiving of the second address step is being performed, writing the first data to the first location of the memory array;

upon completion of the writing of the first data, verifying successful completion of the same;

writing the second data to the second location of the nonvolatile memory array; and

while the writing of the second data step is being performed, receiving a third address for identifying a third location within the nonvolatile memory array where a third data is to be written, thereby creating a pipe-lining affect so as to expedite the performance of write operations of the nonvolatile memory array.