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Multiple-thread processor with single-thread interface shared among threads

  • US 6,801,997 B2
  • Filed: 05/23/2002
  • Issued: 10/05/2004
  • Est. Priority Date: 05/11/1999
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a multiple-thread execution pipeline including a plurality of pipelines respectively allocated to a plurality of execution threads, respective ones of the plurality of pipelines to execute the allocated execution threads in a first thread dimension, wherein at least one of the plurality of pipelines is to execute more than one of the plurality of execution threads in a second thread dimension, and wherein the multiple-thread execution pipeline includes storage elements for holding the plurality of threads;

    a plurality of shared components coupled to the multiple-thread execution pipeline, the shared components being coupled in a sequence so that the plurality of pipelines converge into the sequence of shared components, the shared components being logic components that control but do not hold threads;

    a cache control unit coupled to the multiple-thread execution pipeline;

    an L1 cache coupled to the cache control unit; and

    anti-aliasing logic coupled to the L1 cache so that the L1 cache is shared among threads via anti-aliasing.

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