×

Parameterizable and reconfigurable debugger core generators

  • US 6,802,026 B1
  • Filed: 05/15/2001
  • Issued: 10/05/2004
  • Est. Priority Date: 05/15/2001
  • Status: Active Grant
First Claim
Patent Images

1. A method for debugging a run-time reconfigurable processing arrangement including a processor arrangement coupled to a programmable logic device (PLD), comprising:

  • executing on the processor arrangement a run-time reconfiguration program that includes executable code that specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data, wherein one of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles;

    activating the PLD;

    stepping the PLD for the selected number of clock cycles by the breakpoint circuit on the PLD; and

    checking state information of one or more selected elements of the PLD after stepping the PLD.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×