Parameterizable and reconfigurable debugger core generators
First Claim
1. A method for debugging a run-time reconfigurable processing arrangement including a processor arrangement coupled to a programmable logic device (PLD), comprising:
- executing on the processor arrangement a run-time reconfiguration program that includes executable code that specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data, wherein one of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles;
activating the PLD;
stepping the PLD for the selected number of clock cycles by the breakpoint circuit on the PLD; and
checking state information of one or more selected elements of the PLD after stepping the PLD.
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Abstract
System and method for debugging a run-time reconfigurable processing arrangement. The processing arrangement includes a host process that hosts a run-time reconfiguration application program and a programmable logic device (PLD). The run-time reconfiguration program specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data. One of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles. When the PLD is activated, the breakpoint circuit steps the PLD, and state information of one or more selected elements of the PLD is analyzed after stepping the PLD. Depending on the analysis, the breakpoint core generator is re-parameterized and the PLD reconfigured with a new breakpoint circuit to continue debugging.
142 Citations
19 Claims
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1. A method for debugging a run-time reconfigurable processing arrangement including a processor arrangement coupled to a programmable logic device (PLD), comprising:
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executing on the processor arrangement a run-time reconfiguration program that includes executable code that specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data, wherein one of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles;
activating the PLD;
stepping the PLD for the selected number of clock cycles by the breakpoint circuit on the PLD; and
checking state information of one or more selected elements of the PLD after stepping the PLD. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
associating a new parameter value with the breakpoint circuit after stepping the PLD for the selected number of cycles;
generating new configuration data for the breakpoint circuit with the new parameter value; and
configuring the PLD with the new configuration data.
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5. The method of claim 4, wherein the PLD is configured with the new configuration data by partially reconfiguring the PLD.
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6. The method of claim 1, wherein a portion of the circuit design specifies a tracing circuit that is coupled to and enabled by the breakpoint circuit and coupled to receive selected signals associated with the circuit design, the method further comprising:
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enabling the tracing circuit with a signal from the breakpoint circuit after stepping the PLD for a selected number of clock cycles; and
storing states of the selected signals by the tracing circuit.
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7. The method of claim 1, wherein the portion of the circuit design that specifies the breakpoint circuit is parameterizable by a selected signal with a selected state that triggers stepping the PLD by the breakpoint circuit.
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8. The method of claim 7, further comprising under control of the run-time reconfiguration program:
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associating a new parameter value with the breakpoint circuit after stepping the PLD for the selected number of cycles;
generating new configuration data for the breakpoint circuit with the new parameter value; and
configuring the PLD with the new configuration data.
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9. The method of claim 8, wherein the PLD is configured with the new configuration data by partially reconfiguring the PLD.
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10. The method of claim 1, wherein the portion of the circuit design that specifies the breakpoint circuit is parameterizable by a state transition of a selected signal that triggers stepping the PLD by the breakpoint circuit.
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11. The method of claim 10, further comprising under control of the run-time reconfiguration program:
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associating a new parameter value with the breakpoint circuit after stepping the PLD for the selected number of cycles;
generating new configuration data for the breakpoint circuit with the new parameter value; and
configuring the PLD with the new configuration data.
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12. The method of claim 11, wherein the PLD is configured with the new configuration data by partially reconfiguring the PLD.
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13. An apparatus for debugging a run-time reconfigurable processing arrangement including a processor arrangement coupled to a programmable logic device (PLD), comprising:
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means for generating configuration data that implements a circuit design during execution of a run-time reconfiguration program that specifies the circuit design with references to core generators in a library and configuring the PLD with the configuration data, wherein one of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles;
means for activating the PLD;
means for stepping the PLD for the selected number of clock cycles by the breakpoint circuit on the PLD; and
means for checking state information of one or more selected elements of the PLD after stepping the PLD.
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14. A system for debugging a run-time reconfigurable processing arrangement, comprising:
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a programmable logic device (PLD); and
a processor arrangement coupled to the PLD and hosting a run-time reconfiguration application program, a run-time reconfiguration program interface, and a library of core generators, the run-time reconfiguration program including executable code that, via the program interface, specifies a circuit design with references to core generators in the library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data, wherein one of the core generators referenced by the application program generates a breakpoint circuit that steps the PLD for a selected number of clock cycles. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification