64-bit open firmware implementation and associated api
First Claim
1. A data processing system, comprising:
- a plurality of hardware devices, each one of the plurality of hardware devices operating in a 64-bit mode;
a plurality of operating systems;
a firmware component for virtualizing the plurality of hardware devices for interaction with the plurality of operating systems;
the firmware component being implemented using 64-bits; and
the 64-bit firmware component eliminating virtual addresses and page translations, and rendering virtual address translation from a virtual address to a 64-bit physical address unnecessary.
1 Assignment
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Accused Products
Abstract
An improved logically partitioned data processing system is provided. In one embodiment, the data processing system includes a plurality of hardware devices, including processors, and a plurality of operating systems. Each of the plurality of operating systems executes within a separate partition within the logically partitioned data processing system. A firmware component provides each operating system with a virtualized copy of the hardware devices, thus maintaining separation between each of the logical partitions. The firmware component is implemented as 64-bits, thus allowing each of the processors to execute in 64-bit mode and eliminating the need for virtual address translation from a 32-bit virtual address to a 64-bit physical address.
25 Citations
26 Claims
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1. A data processing system, comprising:
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a plurality of hardware devices, each one of the plurality of hardware devices operating in a 64-bit mode;
a plurality of operating systems;
a firmware component for virtualizing the plurality of hardware devices for interaction with the plurality of operating systems;
the firmware component being implemented using 64-bits; and
the 64-bit firmware component eliminating virtual addresses and page translations, and rendering virtual address translation from a virtual address to a 64-bit physical address unnecessary. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of providing a virtual copy of 64-bit hardware resources within a data processing system to an operating system, the method comprising:
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virtualizing the 64-bit hardware resources using a firmware component that is implemented using 64-bits, the 64-bit firmware component eliminating virtual adds and page translations, and rendering virtual address translation from a via address to a 64-bit physical address unnecessary;
receiving a request to perform an action;
responsive to a determination that values associated with the request are 64-bit quantities, performing the request; and
responsive to a determination that the values associated with the request are 32-bit values, zero extending the values to 64-bit quantities and performing the request using the 64-bit quantities. - View Dependent Claims (10, 11, 12, 13, 14)
responsive to a determination that the requested action is a cache-inhibited action, enabling a cache-inhibited mode within a processor, performing the requested action, and disabling the cache-inhibited mode; and
including a cache within the processor, the cache not being, used when the address is cache-inhibited and the cache being used when the address is not cache-inhibited.
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14. The method as recited in claim 13, wherein a list of address and size pairs that describe cacheable system memory addresses are maintained and an address not falling within one of the address ranges within the list is considered to be a cache-inhibited address.
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15. A computer program product in a computer readable media for use in a data processing system for providing a virtual copy of 64-bit hardware resources within a data processing System to an operating system, the computer program product comprising:
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instructions for virtualizing the 64-bit hardware resources using a firmware component that is implemented using 64-bits, the 64-bit firmware component eliminating virtual addresses and page translations, and rendering virtual address translation from a virtual address to a 64-bit physical address unnecessary;
instructions for receiving a request to perform an action;
instructions, responsive to a determination that values associated with the request are 64-bit quantities, for performing the request; and
instructions, responsive to a determination that the values associated with the request are 32-bit values, for zero extending the values to 64-bit quantities and performing the request using the 64-bit quantities. - View Dependent Claims (16, 17, 18, 19, 20)
instructions, responsive to a determination that the requested action is a cache-inhibited action, for enabling a cache-inhibited mode within a processor, performing the requested action, and disabling the cache-inhibited mode; and
the processor including a cache, the cache not being used when the address is cache-inhibited and the cache being used when the address is not cache-inhibited.
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20. The computer program product as recited in claim 19, wherein a list of address and size pairs that describe cacheable system memory addresses are maintained and an address not falling within one of the address ranges within the list is considered to be a cache-inhibited address.
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21. A system for providing a virtual copy of 64-bit hardware resources within a data processing system to an operating system, the system comprising:
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a firmware component for virtualizing the 64-bit hardware resources, the firmware component being implemented using 64-bits, the 64-bit firmware component eliminating virtual addresses and page translations, and rendering virtual address translation from a virtual address to a 64-bit physical address unnecessary;
first means for receiving a request to perform an action;
second means, responsive to a determination that values associated with the request are 64-bit quantities, for performing the request; and
third means, responsive to a determination that the values associated with the request are 32-bit values, for zero extending the values to 64-bit quantities and performing the request using the 64-bit quantities. - View Dependent Claims (22, 23, 24, 25, 26)
means, responsive to a determination that the requested action is a cache-inhibited action, for enabling a cache-inhibited mode within a processor, performing the requested action, and disabling the cache-inhibited mode; and
the processor including a cache, the cache not being used when the address is cache-inhibited and the cache being used when the address is not cache-inhibited.
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26. The system as recited in claim 25, wherein a list of address and size pairs that describe cacheable system memory addresses are maintained and an address not falling within one of the address ranges within the list is considered to be a cache-inhibited address.
Specification