Method of monitoring contact hole of integrated circuit using corona charges

• US 6,803,241 B2
• Filed: 01/09/2003
• Issued: 10/12/2004
• Est. Priority Date: 01/10/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Eom, Tae-min, Yang, Yu-sin, Jun, Chung-sam
• Primary Examiner(s): Gurley, Lynne A.
• Application Number:
  US10/338,832
• Publication Number:
  US 20030129776A1
• Time in Patent Office: 642 Days
• Field of Search: 438/14, 438/17-18, 438/597-599, 438/637, 438/666
• US Class Current: 438/14
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges over a unit chip having contact holes on a semiconductor wafer; measuring the surface voltage of the unit chip; making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and analyzing the graph to determine whether the contact holes of the unit chip are open. According to the method of the present invention, contact holes may be monitored at an in-line state when manufacturing an integrated circuit by transmitting corona charges onto a unit chip, eliminating the need to use a scanning electronic microscope, thereby preventing a reduction in yield.

Claims

1. A method of monitoring contact holes of an integrated circuit, the method comprising:

transmitting corona charges over a unit chip having contact holes on a semiconductor wafer;

measuring a surface voltage of the unit chip;

making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and

analyzing the graph to determine whether the contact holes of the unit chip are open by determining a saturation level of the surface voltage of the unit chip or by determining if the surface voltage of the unit chip drops.

2. A method of monitoring contact holes of an integrated circuit, the method comprising:

transmitting corona charges over a unit chip having contact holes on a semiconductor wafer;

measuring a surface voltage of the unit chip;

making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip;

determining from the graph whether the measured surface voltage is saturated; and

determining that the contact holes are not open when the measured surface voltage is not saturated and determining whether the contact holes are open when the measured surface voltage is saturated by comparing a measured surface saturation voltage of the unit chip with a predetermined surface saturation voltage of the unit chip.

3. The method of monitoring contact holes as claimed in claim 2, wherein the unit chip comprises a cell array region having contact holes formed by a conventional process, and a peripheral circuit region.

4. The method of monitoring contact holes as claimed in claim 3, wherein the predetermined surface saturation voltage of the unit chip is a surface saturation voltage of a unit chip having open contact holes, and wherein determining whether the contact holes are open is accomplished by analyzing a difference between the measured surface saturation voltage of the unit chip and the predetermined surface saturation voltage of the unit chip, and determining that the contact holes are not open when the measured surface saturation voltage of the unit chip is higher than the predetermined surface saturation voltage of the unit chip.

5. The method of monitoring contact holes as claimed in claim 2, wherein determining whether the contact holes are open is accomplished by analyzing a difference between the measured surface saturation voltage of the unit chip and the predetermined surface saturation voltage of the unit chip.

6. A method of monitoring contact holes of an integrated circuit, the method comprising:

transmitting corona charges over a unit chip having contact holes on a semiconductor wafer;

measuring a surface voltage of the unit chip;

making a graph illustrating a relationship between the amount of corona charges transmitted and the surface voltage of the unit chip;

determining from the graph whether the measured surface voltage is saturated;

determining that the contact holes are not open when the surface voltage is not saturated, and determining whether the surface voltage drops when the surface voltage is saturated; and

determining whether the contact holes are open when the surface voltage drops by analyzing an extent that the surface voltage drops or a period over which the surface voltage drops, and determining whether the contact holes are open when the surface voltage does not drop by comparing a measured surface saturation voltage of the unit chip with a predetermined surface saturation voltage of the unit chip.

7. The method of monitoring contact holes as claimed in claim 6, wherein the unit chip comprises a cell array region in which the contact holes are formed.

8. The method of monitoring contact holes as claimed in claim 6, wherein determining whether the contact holes are open when the surface voltage does not drop is accomplished by analyzing a difference between the measured surface saturation voltage of the unit chip and the predetermined surface saturation voltage of the unit chip.